Design Verification Engineer

🚀 Multiple Design Verification (DV) Opportunities - U.S. Based (Hybrid & Onsite) 🚀

We are partnered with several cutting-edge semiconductor clients who are actively hiring Design Verification Engineers across a range of domains. These roles are NOT fully remote - each has a defined hybrid or onsite expectation, outlined below.

If you’re a DV engineer exploring your next move, chances are one of these aligns well 👇

🔹 Bay Area / Portland / Idaho – Hybrid Model, also open to REMOTE candidates
DV Engineer – SoC Memory Controller
Experience with Memory Controllers
SoC / Full-Chip Level
Strong System Verilog / UVM background

🔹 Bay Area, CA – Hybrid (2–3 days/week)
DV Engineer – Memory Focus
Experience with HBM and/or DDR
Strong SystemVerilog / UVM background
Working on high-performance designs

🔹 New York, NY OR Oregon – Hybrid
DV Engineer (Generalist)
No specific domain specialization required
Solid RTL DV fundamentals (SV/UVM)
2+ years experience

🔹 Bay Area, CA – Hybrid
DV Engineers – Multiple Domains
Looking for DV engineers with experience in one or more of the following:
CPU / Processor
Networking
PCIe / Ethernet
Accelerators
UCIe / CXL
NoC / NIC
FPGA

🔹 Austin, TX – Onsite (4 days/week)
DV Engineer
Experience with ARM or RISC-V
Strong low-power verification background
Hands-on RTL DV role

🔹 Bay Area, CA – Hybrid (2–3 days/week)
CPU Design Verification Lead
10+ years of experience
Strong CPU core background
Multi-core verification experience

🔹 Bay Area, CA – Onsite (Daily)
DV Engineer – PCIe / CXL
Deep experience verifying PCIe and/or CXL
Fully onsite role
8+ years experience
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