MT

Design Verification Engineer

Accepting applications

Mirafra Technologies · Austin, Texas Metropolitan Area

Full-Time Associate ASICDDRPCIePerlPython
Posted
4d ago
Category
Design
Experience
Associate
Country
United States
🚀 Hiring: Design Verification Engineer
📍 Location: San Jose, CA / Austin, TX
💼 Experience: 6+ Years
Requirements:
Strong SystemVerilog & UVM experience
Hands-on ASIC/SoC Design Verification
Experience with Functional/Code Coverage & SVA
Strong constrained-random verification & debugging skills
Experience with VCS/Verdi, Xcelium, or Questa
Knowledge of protocols like AXI, PCIe, DDR is a plus
Scripting experience with Python/Perl/Tcl preferred

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