Design Verification Engineer

Experience with Low power design verification, Formal verification and Gate level simulation.

Knowledge of standard protocols such as PCIe, USB, MIPI, LPDDR, etc., Experience in scripting languages (Python, or Perl).

Experience with mixed-signal IP design verification, such as USB, PCIe, CXL, C2C, D2D, MIPI, UFS, DDR, PLL, Data Convertors (DAC, ADC), or sensors.

Top 5 Required Skills

1. Knowledge of a HVL methodology like SystemVerilog/UVM.

2. Experience working with various ASIC simulation/formal tools such as VCS, Xcellium/NCsim, Modelsim/Questa, VCFormal, Jaspergold, 0In and others.

3. Protocol knowledge of High Speed Serdes external interfaces like PCIe, USB3/4, UFS, MIPI CSI/DSI/HDMI and DDR PHY 4. Would be plus if candidate has working exp on UPF based power aware simulations and Gate level simulations 5. Good at implementing system Verilog assertions and checkers, good debugging skills

Technologies

• Knowledge of standard protocols such as PCIe, USB, MIPI, LPDDR, etc.,

Keywords

• USB, PCIe, CXL, C2C, D2D, MIPI, UFS, DDR, PLL,

Education Requirement

• Master's/Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field

Required Years of Experience

• 5 years ASIC design verification, or related work experience.