Design Verification Engineer

8+ years of experience in SoC Verification with strong proficiency in:
Verilog-HDL
C test development at SoC level
SV Assertions
TCL/Python/Shell scripting
Experience with:
Protocol Knowledge (JTAG, SPI, UART, serial communication protocols and AMBA APB, AHB interconnect protocols)
Gate-level simulation & SDF flows
Coverage tools and methodologies (functional + code coverage)
Hands-on experience debugging complex SoC issues involving ARM subsystems.
Preferred Qualifications
Prior work on mixed-signal or digital-analog interface verification.
Understanding of AHB/APB/AXI interconnects.
Exposure to version control like GitHub Actions, Jenkins, or similar.
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