LI
Design Verification Engineer
Accepting applicationsLanceSoft, Inc. · Austin, TX
Contract Mid_senior ASICC++PerlRTLSoC
Posted
1d ago
Category
Verification
Experience
Mid_senior
Country
United States
Pay Rate: $70.00/hr to $80.00/hr
Duration: 12 Months
Location: Austin, TX
JOB DUTIES:
Participate in the functional verification of a block(s) of complex ASICs and/or IP cores for a combined CPU/GPU development effort.
Be part of a team of design and verification engineers, working closely with other team members to understand and verify the functionality of a given design element within the context of the block, chip and overall system.
Be responsible for carefully documenting and executing test plan(s) consisting of directed and constrained-random tests to be run during simulation.
Be expected to adopt the evolving verification methodologies used in the industry to functionally verify increasingly more complex SoC designs within aggressive, market-driven schedules, and work within the existing verification infrastructure on currently active projects.
Be familiar with hardware modeling and/or assertion-based verification methods.
EXPERIENCE AND EDUCATION:
8-10 years of proven verification experience on large ASIC development projects or software/firmware experience in a hardware development setting;
Strong background in C/C++ development in a Linux Environment;
Strong debug skills and experience with debug tools such as Gdb, Valgrind;
Proficient in Object Oriented programming, STL, computer architecture and data structures;
Knowledge of Perl and Makefiles;
Experience in Verilog/SystemVerilog/SystemC, preferred;
Experience in C/Verilog environment using DPI/PLI, preferred;
Strong analytical skills and attention to detail;
Excellent written and communication skills
Must-Have Requirements
8–10+ years of hand-on Design Verification experience in IP/Sub-system environments.
Expertise in SystemVerilog and UVM-based verification methodologies.
Solid experience developing verification plans, testbenches, sequences, monitors, scoreboards, and coverage models.
Strong debugging skills across RTL, testbench, and simulation failures.
Strong execution mindset with a proven ability to independently drive verification tasks to closure.
Nice-to-Have Requirements
Experience with fabric / interconnect / coherency / high‑performance data path designs.
Familiarity with multiple configurations, scalability challenges, or parameterized environments.
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Duration: 12 Months
Location: Austin, TX
JOB DUTIES:
Participate in the functional verification of a block(s) of complex ASICs and/or IP cores for a combined CPU/GPU development effort.
Be part of a team of design and verification engineers, working closely with other team members to understand and verify the functionality of a given design element within the context of the block, chip and overall system.
Be responsible for carefully documenting and executing test plan(s) consisting of directed and constrained-random tests to be run during simulation.
Be expected to adopt the evolving verification methodologies used in the industry to functionally verify increasingly more complex SoC designs within aggressive, market-driven schedules, and work within the existing verification infrastructure on currently active projects.
Be familiar with hardware modeling and/or assertion-based verification methods.
EXPERIENCE AND EDUCATION:
8-10 years of proven verification experience on large ASIC development projects or software/firmware experience in a hardware development setting;
Strong background in C/C++ development in a Linux Environment;
Strong debug skills and experience with debug tools such as Gdb, Valgrind;
Proficient in Object Oriented programming, STL, computer architecture and data structures;
Knowledge of Perl and Makefiles;
Experience in Verilog/SystemVerilog/SystemC, preferred;
Experience in C/Verilog environment using DPI/PLI, preferred;
Strong analytical skills and attention to detail;
Excellent written and communication skills
Must-Have Requirements
8–10+ years of hand-on Design Verification experience in IP/Sub-system environments.
Expertise in SystemVerilog and UVM-based verification methodologies.
Solid experience developing verification plans, testbenches, sequences, monitors, scoreboards, and coverage models.
Strong debugging skills across RTL, testbench, and simulation failures.
Strong execution mindset with a proven ability to independently drive verification tasks to closure.
Nice-to-Have Requirements
Experience with fabric / interconnect / coherency / high‑performance data path designs.
Familiarity with multiple configurations, scalability challenges, or parameterized environments.
Show more Show less