IP
Design Verification Engineer
Accepting applicationsIntegrated Personnel Services Limited · California, United States
Full-Time Mid_senior ASICATEFPGARTLUVM
Posted
2d ago
Category
Verification
Experience
Mid_senior
Country
United States
Role: Design Verification Engineer
Location: San Jose, CA/ Irvine, CA / San Diego, CA (Onsite)
Type: Full Time Permanent
Job Description
Architect block and full-chip verification environments using HVLs and constrained random techniques for SOCs with embedded CPUs and mixed signal interfaces. Requires UVM, System Verilog, and SVA.
Develop test plans and coverage metrics from specifications and write block and chip-level
tests in C, SV, and UVM.
Debug RTL and Gate simulations and work with design engineers to verify fixes.
Write diagnostics for validating the FPGA prototype (pre-tapeout) and the ASIC.
Replicate silicon bugs in simulation environments and validate fixes or SW workarounds.
Convert verification tests into test patterns and assist Test Engineers with ATE vector bring-up.
Evaluate the latest verification methodologies and develop scripts, etc., to automate verification flows.
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Location: San Jose, CA/ Irvine, CA / San Diego, CA (Onsite)
Type: Full Time Permanent
Job Description
Architect block and full-chip verification environments using HVLs and constrained random techniques for SOCs with embedded CPUs and mixed signal interfaces. Requires UVM, System Verilog, and SVA.
Develop test plans and coverage metrics from specifications and write block and chip-level
tests in C, SV, and UVM.
Debug RTL and Gate simulations and work with design engineers to verify fixes.
Write diagnostics for validating the FPGA prototype (pre-tapeout) and the ASIC.
Replicate silicon bugs in simulation environments and validate fixes or SW workarounds.
Convert verification tests into test patterns and assist Test Engineers with ATE vector bring-up.
Evaluate the latest verification methodologies and develop scripts, etc., to automate verification flows.
Show more Show less