IS
Design Verification Engineer
Accepting applicationsInfobahn Softworld Inc · Santa Clara, CA
Contract Mid_senior DDREthernetPCIeSystemVerilogUSB
Posted
4d ago
Category
Verification
Experience
Mid_senior
Country
United States
Title: Design Verification Engineer
Location: Santa Clara - Onsite
Top Skills: SystemVerilog UVM; IP design verification; Physical (PHY) layer; SoCs
THE ROLE:
We are seeking a seasoned verification lead with expertise or significant interest in IO/PHY verification. You have had significant success driving IP verification, UVM and SystemVerilog. This senior role will stretch you as you lead DV teams in new directions, network with our world-class design/DV teams.
KEY RESPONSIBILITIES:
Define verification plan, and provide technical direction to execution teams
Comprehend AMS, Firmware and design spec. Work with other functional leads to come up with a DV plan and execute the plan.
Create UVM/SystemVerilog based testbenches and tests.
Make sure that design is bug free.
Lead Formal verification.
Understanding interface standards such as PCIe, USB, DDR/LPDDR memory, Ethernet
Support Post-Silicon teams for Product Performance, Power and functional issues debug/resolution
PREFERRED EXPERIENCE:
IO/PHY knowledge.
Formal verification expertise.
Firmware experience.
Excellent communication, management, and presentation skills.
Adept at collaboration among top-thinkers and senior architects with strong interpersonal skills to work across teams in different geographies
ACADEMIC CREDENTIALS:
Bachelor’s or Master’s degree in related discipline preferred
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Location: Santa Clara - Onsite
Top Skills: SystemVerilog UVM; IP design verification; Physical (PHY) layer; SoCs
THE ROLE:
We are seeking a seasoned verification lead with expertise or significant interest in IO/PHY verification. You have had significant success driving IP verification, UVM and SystemVerilog. This senior role will stretch you as you lead DV teams in new directions, network with our world-class design/DV teams.
KEY RESPONSIBILITIES:
Define verification plan, and provide technical direction to execution teams
Comprehend AMS, Firmware and design spec. Work with other functional leads to come up with a DV plan and execute the plan.
Create UVM/SystemVerilog based testbenches and tests.
Make sure that design is bug free.
Lead Formal verification.
Understanding interface standards such as PCIe, USB, DDR/LPDDR memory, Ethernet
Support Post-Silicon teams for Product Performance, Power and functional issues debug/resolution
PREFERRED EXPERIENCE:
IO/PHY knowledge.
Formal verification expertise.
Firmware experience.
Excellent communication, management, and presentation skills.
Adept at collaboration among top-thinkers and senior architects with strong interpersonal skills to work across teams in different geographies
ACADEMIC CREDENTIALS:
Bachelor’s or Master’s degree in related discipline preferred
Show more Show less