H
Design Verification Engineer
Accepting applicationsHappieHire · Greater Bengaluru Area
Full-Time Mid_senior ASICATPGDFTMentorPerl
Posted
1d ago
Category
Verification
Experience
Mid_senior
Country
India
Role: Design Verification / GLS Engineer
Location: Bangalore
Experience: 5–10 Years
Work Mode: Work from Office
Working Days: 5 Days Office
Employment Type: Full-Time
Role Overview:
We are looking for an experienced Design Verification / GLS Engineer with 8–10 years of hands-on experience in ASIC/SoC Design Verification and Gate-Level Simulation (GLS). The ideal candidate will be responsible for developing and executing verification strategies, testbenches, simulations, and GLS validation for complex semiconductor designs.
Key Responsibilities:
Own and execute verification activities at block, subsystem, and SoC levels.
Develop and maintain SystemVerilog/UVM-based verification environments.
Create test plans, test scenarios, test cases, and functional coverage plans.
Perform RTL simulation, regression, debug, and coverage analysis.
Drive Gate-Level Simulation (GLS) activities, including post-synthesis and post-P&R simulations.
Debug GLS failures related to timing, SDF annotation, X-propagation, reset, clocking, and functional issues.
Analyze simulation failures and work closely with RTL, Design, Synthesis, STA, and Physical Design teams.
Develop and maintain directed and constrained-random tests.
Ensure functional and code coverage closure.
Participate in verification planning, reviews, and sign-off activities.
Automate verification and regression flows using Python, Perl, Shell, or Tcl.
Support continuous improvement of verification methodologies, infrastructure, and debug processes.
Mentor junior verification engineers and provide technical guidance.
Required Skills:
5–10 years of experience in ASIC/SoC Design Verification.]
Strong hands-on experience in Gate-Level Simulation (GLS).
Strong proficiency in SystemVerilog and UVM.
Experience with RTL simulation and functional verification.
Good understanding of SDF, timing checks, back-annotation, and X-propagation.
Experience with simulation/debug tools such as VCS, Questa/ModelSim, or equivalent.
Strong understanding of ASIC/SoC verification methodologies and verification sign-off.
Experience with coverage analysis and regression management.
Good scripting/programming skills in Python, Perl, Tcl, or Shell.
Good understanding of digital design concepts, clock/reset architecture, and timing.
Strong debugging and problem-solving skills.
Good to Have:
Experience with post-synthesis and post-layout GLS.
Knowledge of STA and timing constraints.
Experience with UPF/low-power verification.
Exposure to DFT, scan, MBIST/LBIST, or ATPG-related verification.
Experience working on complex SoC/CPU/ASIC projects.
Familiarity with Linux-based verification environments and CI/regression frameworks.
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Location: Bangalore
Experience: 5–10 Years
Work Mode: Work from Office
Working Days: 5 Days Office
Employment Type: Full-Time
Role Overview:
We are looking for an experienced Design Verification / GLS Engineer with 8–10 years of hands-on experience in ASIC/SoC Design Verification and Gate-Level Simulation (GLS). The ideal candidate will be responsible for developing and executing verification strategies, testbenches, simulations, and GLS validation for complex semiconductor designs.
Key Responsibilities:
Own and execute verification activities at block, subsystem, and SoC levels.
Develop and maintain SystemVerilog/UVM-based verification environments.
Create test plans, test scenarios, test cases, and functional coverage plans.
Perform RTL simulation, regression, debug, and coverage analysis.
Drive Gate-Level Simulation (GLS) activities, including post-synthesis and post-P&R simulations.
Debug GLS failures related to timing, SDF annotation, X-propagation, reset, clocking, and functional issues.
Analyze simulation failures and work closely with RTL, Design, Synthesis, STA, and Physical Design teams.
Develop and maintain directed and constrained-random tests.
Ensure functional and code coverage closure.
Participate in verification planning, reviews, and sign-off activities.
Automate verification and regression flows using Python, Perl, Shell, or Tcl.
Support continuous improvement of verification methodologies, infrastructure, and debug processes.
Mentor junior verification engineers and provide technical guidance.
Required Skills:
5–10 years of experience in ASIC/SoC Design Verification.]
Strong hands-on experience in Gate-Level Simulation (GLS).
Strong proficiency in SystemVerilog and UVM.
Experience with RTL simulation and functional verification.
Good understanding of SDF, timing checks, back-annotation, and X-propagation.
Experience with simulation/debug tools such as VCS, Questa/ModelSim, or equivalent.
Strong understanding of ASIC/SoC verification methodologies and verification sign-off.
Experience with coverage analysis and regression management.
Good scripting/programming skills in Python, Perl, Tcl, or Shell.
Good understanding of digital design concepts, clock/reset architecture, and timing.
Strong debugging and problem-solving skills.
Good to Have:
Experience with post-synthesis and post-layout GLS.
Knowledge of STA and timing constraints.
Experience with UPF/low-power verification.
Exposure to DFT, scan, MBIST/LBIST, or ATPG-related verification.
Experience working on complex SoC/CPU/ASIC projects.
Familiarity with Linux-based verification environments and CI/regression frameworks.
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