Design Verification Engineer

Role: Design Verification Engineer
Location: San Jose, CA (On-site)
Experience: 7+ years
---
Eximietas Design is looking for talented Design Verification Engineers to work on cutting-edge AI hardware — building next-generation inference systems purpose-built for transformer models. This is an opportunity to take end-to-end ownership of critical IP subsystems and help bring advanced silicon to life.

This is a hands-on role — strong coding skills are a must.
---
What You'll Be Working On:

- Architecting and developing sophisticated UVM/SystemVerilog verification environments for both custom and vendor IP blocks
- Building comprehensive verification plans that address functional correctness, performance validation, concurrency scenarios, and corner-case coverage
- Verifying complex subsystems including PCIe, Ethernet, AXI/AMBA interfaces, CPU architectures, DMA engines, memory subsystems, Network-on-Chip (NoC), and high-throughput compute arrays
- Debugging intricate datapath and protocol issues across RTL and testbench environments
- Driving coverage metrics analysis to ensure silicon-ready quality
- Collaborating closely with architects, RTL designers, software teams, firmware engineers, and emulation teams to validate end-to-end functionality
- Contributing to reusable DV infrastructure and methodology improvements that scale with the team

---
What You Bring:

- Strong hands-on experience with UVM methodology and SystemVerilog testbench design
- Proven track record verifying complex digital designs — datapaths, memory systems, interconnects, or high-throughput fabrics
- Experience with standard protocols such as PCIe, Ethernet, AXI/AMBA, or ARM/ARC CPU architectures
- Solid foundation in computer architecture and digital design fundamentals
- Strong debugging and problem-solving skills with the ability to dive deep into complex issues
- Excellent cross-functional collaboration skills — you'll be working across multiple teams
- Self-driven mindset with the ability to thrive in a fast-paced startup environment

---
Bonus Points For:

- Experience with vendor IP integration and VIP environments
- SystemVerilog Assertions (SVA) and formal verification expertise
- Background verifying AI/ML accelerators, systolic arrays, or similar compute-intensive architectures
- Scripting skills (Python, Perl, TCL) for automation and regression flows

---
Why Join?

- Work on hard problems at the intersection of AI and silicon
- Collaborative, high-impact environment with world-class engineers

---
Interested? Let's connect!

📧 mohini.tyagi@eximietas.design
Show more Show less