DS
Design Verification Engineer
Accepting applicationsDragonX Systems · Delhi, India
Full-Time Entry PythonRTLSystemVerilogUVMVerilog
Estimated market salary
₹4-6 LPA
This is a SiliconBoard market estimate, not an employer-posted salary.
Posted
20h ago
Category
Verification
Experience
Entry
Country
India
Company Description DragonX Systems is a US-based EDA startup focused on building next-generation tools for chip design and system simulation for global enterprises. The company offers opportunities to work on challenging, high-impact problems that advance the state of the art in semiconductor design. Team members see their work deployed to real customers and gain visibility in the global chip industry. Employees learn directly from experienced technical leadership, including a Stanford PhD with deep EDA expertise, in a fast-paced startup environment with a strong global vision.
Role Description The Design Verification Engineer will be responsible for verifying complex digital designs and ensuring that DragonX Systems’ chip design and simulation tools meet rigorous quality and performance standards. Day-to-day tasks include developing verification plans, building and maintaining testbenches, writing and executing test cases, performing formal and functional verification, and analyzing coverage and results to identify defects and edge cases. The engineer will collaborate closely with RTL design, architecture, and software teams to understand specifications, review designs, and drive issues to resolution through systematic debugging. This is a full-time, on-site role based in Guwahati, requiring active engagement with local team members and participation in design reviews, tool evaluations, and continuous improvement of verification methodologies.
Qualifications
Strong expertise in Formal Verification and Functional Verification of complex digital systems, with the ability to develop comprehensive verification strategies and test plans.
Solid RTL Design and Computer Architecture knowledge, with the ability to understand specifications and translate them into effective verification scenarios and test cases.
Hands-on experience with Verilog/SystemVerilog, UVM, and SystemVerilog Assertions (SVA) for developing robust simulation-based verification environments.
Develop directed and constrained-random tests, verification components such as drivers, monitors, scoreboards, checkers, and sequences, and drive functional and coverage closure.
Strong debugging and root-cause analysis skills across RTL, testbenches, simulation failures, and verification environments.
Experience with EDA tools, simulation environments, regression flows, version control, and scripting/automation using Python, Shell, or similar languages.
Strong analytical, communication, and collaboration skills, with the ability to work effectively in a fast-paced, cross-functional hardware engineering environment.
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Role Description The Design Verification Engineer will be responsible for verifying complex digital designs and ensuring that DragonX Systems’ chip design and simulation tools meet rigorous quality and performance standards. Day-to-day tasks include developing verification plans, building and maintaining testbenches, writing and executing test cases, performing formal and functional verification, and analyzing coverage and results to identify defects and edge cases. The engineer will collaborate closely with RTL design, architecture, and software teams to understand specifications, review designs, and drive issues to resolution through systematic debugging. This is a full-time, on-site role based in Guwahati, requiring active engagement with local team members and participation in design reviews, tool evaluations, and continuous improvement of verification methodologies.
Qualifications
Strong expertise in Formal Verification and Functional Verification of complex digital systems, with the ability to develop comprehensive verification strategies and test plans.
Solid RTL Design and Computer Architecture knowledge, with the ability to understand specifications and translate them into effective verification scenarios and test cases.
Hands-on experience with Verilog/SystemVerilog, UVM, and SystemVerilog Assertions (SVA) for developing robust simulation-based verification environments.
Develop directed and constrained-random tests, verification components such as drivers, monitors, scoreboards, checkers, and sequences, and drive functional and coverage closure.
Strong debugging and root-cause analysis skills across RTL, testbenches, simulation failures, and verification environments.
Experience with EDA tools, simulation environments, regression flows, version control, and scripting/automation using Python, Shell, or similar languages.
Strong analytical, communication, and collaboration skills, with the ability to work effectively in a fast-paced, cross-functional hardware engineering environment.
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