CI

Design Verification Engineer

Accepting applications

COGENT Infotech · Saratoga, CA

Contract Mid_senior PerlPythonSoCSystemVerilogUVM
Posted
14 Aug
Category
Verification
Experience
Mid_senior
Country
United States
Job Title: Design Verification Engineer

Location: Saratoga, CA (Onsite)-5 days

Job Description
We are seeking a Design Verification Engineer with 8+ years of experience in semiconductor verification. The ideal candidate will have strong expertise in SystemVerilog and proven experience in verifying complex IPs and SoCs.
Key Responsibilities & Requirements
8+ years of hands-on experience in Design Verification for IP and SoC-level designs.
Strong proficiency in SystemVerilog for developing verification environments, testbenches, assertions, and testcases.
Strong understanding of verification methodologies and industry best practices.
Experience with UVM and scripting languages such as Python, Perl, or Shell.
Experience in planning and executing functional verification strategies for complex digital designs.
Ability to debug and resolve design and verification issues through close collaboration with design and architecture teams.

If interested in the above please share the below:-
Your Updated Resume with contact details
Your minimum hourly rate expectation :________
Your availability to connect on call. ___________
Work Authorization._______

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