AI
Design Verification Engineer
Accepting applicationsAvanciers Inc. · United States
Full-Time Mid_senior CadenceMentorPerlRTLSystemVerilog
Posted
2d ago
Category
Verification
Experience
Mid_senior
Country
United States
Avanciers is seeking a highly skilled Design Verification Engineer for an exciting opportunity with one of our Fortune 500 clients, based in USA (Remote).
Role: Design Verification Engineer (Data Fabric Verification Engineer)
Location: Remote – USA
We are looking for skilled Design Verification Engineers with strong expertise in SystemVerilog, UVM, RTL, and Formal Verification to join an advanced hardware verification team working on high-performance data fabric and interconnect architectures.
This is an excellent opportunity to work closely with architects, RTL designers, and silicon validation teams on cutting-edge verification environments and architecture-level designs.
Key Skills Required
Strong hands-on experience in SystemVerilog and UVM
Experience building complex verification environments
Strong understanding of RTL design and verification
Expertise in Formal Verification
Knowledge of computer architecture and interconnect/fabric designs
Experience with verification tools Like VCS, Cadence, Mentor Graphics
Scripting knowledge in Perl, Ruby, Make, or similar tools is a plus
Responsibilities
Develop and execute verification test plans
Write tests, sequences, assertions, and testbench components using SystemVerilog and UVM
Drive formal verification activities for design blocks
Work closely with RTL and architecture teams to validate design functionality
Analyze coverage metrics including code and functional coverage
Debug and resolve complex design and verification issues
Collaborate with cross-functional engineering teams throughout the development cycle
Preferred Background
Experience with fabric/interconnect or architecture-level verification
Exposure to post-silicon validation environments
Bachelor’s or Master’s degree in Computer Engineering, Electrical Engineering, or related field
Show more Show less
Role: Design Verification Engineer (Data Fabric Verification Engineer)
Location: Remote – USA
We are looking for skilled Design Verification Engineers with strong expertise in SystemVerilog, UVM, RTL, and Formal Verification to join an advanced hardware verification team working on high-performance data fabric and interconnect architectures.
This is an excellent opportunity to work closely with architects, RTL designers, and silicon validation teams on cutting-edge verification environments and architecture-level designs.
Key Skills Required
Strong hands-on experience in SystemVerilog and UVM
Experience building complex verification environments
Strong understanding of RTL design and verification
Expertise in Formal Verification
Knowledge of computer architecture and interconnect/fabric designs
Experience with verification tools Like VCS, Cadence, Mentor Graphics
Scripting knowledge in Perl, Ruby, Make, or similar tools is a plus
Responsibilities
Develop and execute verification test plans
Write tests, sequences, assertions, and testbench components using SystemVerilog and UVM
Drive formal verification activities for design blocks
Work closely with RTL and architecture teams to validate design functionality
Analyze coverage metrics including code and functional coverage
Debug and resolve complex design and verification issues
Collaborate with cross-functional engineering teams throughout the development cycle
Preferred Background
Experience with fabric/interconnect or architecture-level verification
Exposure to post-silicon validation environments
Bachelor’s or Master’s degree in Computer Engineering, Electrical Engineering, or related field
Show more Show less