A
Design Verification Engineer
Accepting applicationsAscendion · Sunnyvale, CA
Full-Time Mid_senior AIPerlPythonRTLSystemVerilog
Posted
1d ago
Category
Verification
Experience
Mid_senior
Country
United States
About Ascendion
Ascendion is an AI-native software engineering disruptor helping businesses innovate faster, smarter, and with greater impact. We partner with enterprise clients across North America, the UK, Europe, and APAC to solve complex challenges in data, experience design, software product engineering, and workforce transformation. Powered by expert engineers, thousands of AI agents, and our Engineering to the Power of AI (EngineeringAI) method, we deliver measurable outcomes that build trust, unlock value, and accelerate growth.
Learn more at https://ascendion.com/.
Engineering to the Power of AI™, AAVA™, EngineeringAI, Engineering to Elevate Life™, Enterprise PlatformsAI, Data & InsightsAI, ExperienceAI, GCCAI, OperationsAI, Platform EngineeringAI, ProductAI, and Quality EngineeringAIare trademarks or service marks of Ascendion®. AAVA™ is pending registration. Unauthorized use is strictly prohibited.
Ascendion | Engineering to elevate life
We have a culture built on opportunity, inclusion, and a spirit of partnership. Come, change the world with us:
Build the coolest tech for the world’s leading brands
Solve complex problems - and learn new skills
Experience the power of transforming digital engineering for Fortune 500 clients
Master your craft with leading training programs and hands-on experience
Experience a community of change makers!
Join a culture of high-performing innovators with endless ideas and a passion for tech. Our culture is the fabric of our company, and it is what makes us unique and diverse. The way we share ideas, learning, experiences, successes, and joy allows everyone to be their best at Ascendion.
About the Role
Location: Sunnyvale, CA (3 days onsite)
Responsibilities:
Develop and execute verification plans for RTL blocks/IPs across the subsystem.
Build and maintain SystemVerilog/UVM testbenches; write directed and constrained-random tests.
Drive functional coverage and assertion (SVA) closure; run and triage regressions.
Perform power/performance measurement across design stages using PPA RTL, PtPx tool; correlate results with post silicon and feed back to design/power-modeling teams.
Build power/perf dashboard for tracking and publishing.
Debug RTL failures (waveform/Verdi) and provide actionable feedback to the design team/verification team.
Contribute to automation of verification/regression and power/performance measurement flows (Python).
Required Skills:
Proven SystemVerilog + UVM verification experience (testbench architecture, sequences, drivers/monitors).
Functional coverage, constrained-random, and assertion-based verification (SVA); coverage closure.
Strong RTL debug with industry simulators (VCS / Xcelium / Questa) and waveform tools (Verdi).
Working knowledge of RTL design principles and digital design fundamentals.
Proficiency in Python (or Perl) scripting for automation.
Desirable Skills:
Experience with power measurement tools — PrimeTime PX (PTPX) or equivalent (e.g., PrimePower).
Low-power / power-aware verification (UPF, power-aware sim) in advanced nodes (7nm and below).
Formal verification and/or emulation (Palladium / Zebu) experience.
Familiarity with the RTL-to-GDSII flow.
Data analysis / ML approaches for coverage or debug triage.
Education Qualification:
BS in Electrical/Computer Engineering or Computer Science required; MS preferred (not required).
Top 3 Must-Have Skills:
SystemVerilog / UVM testbench development.
Functional coverage + assertion-based verification and coverage closure.
RTL debug (VCS/Xcelium) + Python automation; power/perf measurement.
Salary and Other Compensation: The salary for this position is between $165,000 - $175,000 USD annually. Factors which may affect pay within this range may include geography/market, skills, education, experience, and other qualifications of the successful candidate.
Benefits: The Company offers the following benefits for this position, subject to applicable eligibility requirements: [medical insurance] [dental insurance] [vision insurance] [401(k) retirement plan] [long-term disability insurance] [short-term disability insurance] [5 personal days accrued each calendar year. The Paid time off benefits meet the paid sick and safe time laws that pertains to the City/ State] [10-15 days of paid vacation time] [6 paid holidays and 1 floating holiday per calendar year] [Ascendion Learning Management System]
Want to change the world? Let us know.
Tell us about your experiences, education, and ambitions. Bring your knowledge, unique viewpoint, and creativity to the table. Let’s talk!
Show more Show less
Ascendion is an AI-native software engineering disruptor helping businesses innovate faster, smarter, and with greater impact. We partner with enterprise clients across North America, the UK, Europe, and APAC to solve complex challenges in data, experience design, software product engineering, and workforce transformation. Powered by expert engineers, thousands of AI agents, and our Engineering to the Power of AI (EngineeringAI) method, we deliver measurable outcomes that build trust, unlock value, and accelerate growth.
Learn more at https://ascendion.com/.
Engineering to the Power of AI™, AAVA™, EngineeringAI, Engineering to Elevate Life™, Enterprise PlatformsAI, Data & InsightsAI, ExperienceAI, GCCAI, OperationsAI, Platform EngineeringAI, ProductAI, and Quality EngineeringAIare trademarks or service marks of Ascendion®. AAVA™ is pending registration. Unauthorized use is strictly prohibited.
Ascendion | Engineering to elevate life
We have a culture built on opportunity, inclusion, and a spirit of partnership. Come, change the world with us:
Build the coolest tech for the world’s leading brands
Solve complex problems - and learn new skills
Experience the power of transforming digital engineering for Fortune 500 clients
Master your craft with leading training programs and hands-on experience
Experience a community of change makers!
Join a culture of high-performing innovators with endless ideas and a passion for tech. Our culture is the fabric of our company, and it is what makes us unique and diverse. The way we share ideas, learning, experiences, successes, and joy allows everyone to be their best at Ascendion.
About the Role
Location: Sunnyvale, CA (3 days onsite)
Responsibilities:
Develop and execute verification plans for RTL blocks/IPs across the subsystem.
Build and maintain SystemVerilog/UVM testbenches; write directed and constrained-random tests.
Drive functional coverage and assertion (SVA) closure; run and triage regressions.
Perform power/performance measurement across design stages using PPA RTL, PtPx tool; correlate results with post silicon and feed back to design/power-modeling teams.
Build power/perf dashboard for tracking and publishing.
Debug RTL failures (waveform/Verdi) and provide actionable feedback to the design team/verification team.
Contribute to automation of verification/regression and power/performance measurement flows (Python).
Required Skills:
Proven SystemVerilog + UVM verification experience (testbench architecture, sequences, drivers/monitors).
Functional coverage, constrained-random, and assertion-based verification (SVA); coverage closure.
Strong RTL debug with industry simulators (VCS / Xcelium / Questa) and waveform tools (Verdi).
Working knowledge of RTL design principles and digital design fundamentals.
Proficiency in Python (or Perl) scripting for automation.
Desirable Skills:
Experience with power measurement tools — PrimeTime PX (PTPX) or equivalent (e.g., PrimePower).
Low-power / power-aware verification (UPF, power-aware sim) in advanced nodes (7nm and below).
Formal verification and/or emulation (Palladium / Zebu) experience.
Familiarity with the RTL-to-GDSII flow.
Data analysis / ML approaches for coverage or debug triage.
Education Qualification:
BS in Electrical/Computer Engineering or Computer Science required; MS preferred (not required).
Top 3 Must-Have Skills:
SystemVerilog / UVM testbench development.
Functional coverage + assertion-based verification and coverage closure.
RTL debug (VCS/Xcelium) + Python automation; power/perf measurement.
Salary and Other Compensation: The salary for this position is between $165,000 - $175,000 USD annually. Factors which may affect pay within this range may include geography/market, skills, education, experience, and other qualifications of the successful candidate.
Benefits: The Company offers the following benefits for this position, subject to applicable eligibility requirements: [medical insurance] [dental insurance] [vision insurance] [401(k) retirement plan] [long-term disability insurance] [short-term disability insurance] [5 personal days accrued each calendar year. The Paid time off benefits meet the paid sick and safe time laws that pertains to the City/ State] [10-15 days of paid vacation time] [6 paid holidays and 1 floating holiday per calendar year] [Ascendion Learning Management System]
Want to change the world? Let us know.
Tell us about your experiences, education, and ambitions. Bring your knowledge, unique viewpoint, and creativity to the table. Let’s talk!
Show more Show less