AT
Design Verification Engineer
Accepting applicationsAcceler8 Talent · San Francisco Bay Area
Full-Time Mid_senior AIASICDFTRTLSoC
Posted
4d ago
Category
Design
Experience
Mid_senior
Country
United States
Senior ASIC Design Engineer - (open from junior to senior)
Santa Clara, CA or Boston, MA (Onsite x5 days a week )
Up to $250k + Bonus + Equity
I'm working with an early-stage semiconductor company building a new category of AI infrastructure.
As AI models continue to scale, compute is no longer the only bottleneck—memory has become one of the biggest challenges limiting performance. Instead of solving that problem by adding more GPUs, this team is taking a fundamentally different approach.
They're developing the world's first Memory Processing Unit (MPU), using high-speed optical interconnects to decouple memory from compute and dramatically expand the amount of memory AI systems can access. Their architecture enables existing GPU clusters to scale far beyond today's limitations without requiring developers to rewrite software or rebuild data centre infrastructure.
It's a chance to work on technology that sits at the intersection of silicon, computer architecture, memory systems, and AI infrastructure, alongside a team with deep expertise across semiconductors, photonics, and high-performance computing.
You'll work on:
Designing RTL for next-generation IP, subsystems, and SoCs
Developing microarchitecture for high-performance memory acceleration hardware
Optimising designs for power, performance, and area (PPA)
Driving silicon development from architecture through tapeout
Collaborating closely with verification, physical design, firmware, and post-silicon teams
Influencing technical direction within a small, highly experienced engineering team
We're looking for engineers who have:
5+ years of ASIC or SoC digital design experience
Strong RTL design experience using Verilog or SystemVerilog
Experience developing microarchitecture for complex silicon
Taken ASICs or SoCs through the full development lifecycle, including tapeout
Experience optimising designs for performance, power, and area
Enjoy building complex hardware in a fast-moving, collaborative environment
Nice to have:
AI accelerator or datacentre silicon experience
Memory subsystem or interconnect design
DFT or post-silicon validation experience
Experience working with external IP vendors or foundries
Startup experience
If you're excited by solving fundamental hardware challenges and building the next generation of AI infrastructure, I'd love to chat.
Show more Show less
Santa Clara, CA or Boston, MA (Onsite x5 days a week )
Up to $250k + Bonus + Equity
I'm working with an early-stage semiconductor company building a new category of AI infrastructure.
As AI models continue to scale, compute is no longer the only bottleneck—memory has become one of the biggest challenges limiting performance. Instead of solving that problem by adding more GPUs, this team is taking a fundamentally different approach.
They're developing the world's first Memory Processing Unit (MPU), using high-speed optical interconnects to decouple memory from compute and dramatically expand the amount of memory AI systems can access. Their architecture enables existing GPU clusters to scale far beyond today's limitations without requiring developers to rewrite software or rebuild data centre infrastructure.
It's a chance to work on technology that sits at the intersection of silicon, computer architecture, memory systems, and AI infrastructure, alongside a team with deep expertise across semiconductors, photonics, and high-performance computing.
You'll work on:
Designing RTL for next-generation IP, subsystems, and SoCs
Developing microarchitecture for high-performance memory acceleration hardware
Optimising designs for power, performance, and area (PPA)
Driving silicon development from architecture through tapeout
Collaborating closely with verification, physical design, firmware, and post-silicon teams
Influencing technical direction within a small, highly experienced engineering team
We're looking for engineers who have:
5+ years of ASIC or SoC digital design experience
Strong RTL design experience using Verilog or SystemVerilog
Experience developing microarchitecture for complex silicon
Taken ASICs or SoCs through the full development lifecycle, including tapeout
Experience optimising designs for performance, power, and area
Enjoy building complex hardware in a fast-moving, collaborative environment
Nice to have:
AI accelerator or datacentre silicon experience
Memory subsystem or interconnect design
DFT or post-silicon validation experience
Experience working with external IP vendors or foundries
Startup experience
If you're excited by solving fundamental hardware challenges and building the next generation of AI infrastructure, I'd love to chat.
Show more Show less