MT
Design Verification Engineer 4Y to 10Y (Bangalore)
Accepting applicationsMirafra Technologies · Bengaluru, Karnataka, India
Full-Time Entry ARMATPGBoundary ScanC++DFT
Estimated market salary
₹3-6 LPA
This is a SiliconBoard market estimate, not an employer-posted salary.
Posted
19h ago
Category
Verification
Experience
Entry
Country
India
Company Description Mirafra Technologies is a technology consulting company specializing in semiconductor design services, embedded software development, and digital transformation. The company has a strong team of over 1,000 engineers and is headquartered in Bangalore, with additional offices in Hyderabad, Chennai, and Pune. Mirafra also has a growing international presence with teams in the United States, Singapore, and Sweden. Its engineers have delivered hundreds of successful projects and are known for solving complex technical challenges while receiving continuous training and development. Mirafra maintains long-term partnerships with customers ranging from startups to leading global semiconductor companies.
Role Description This is a full-time, on-site Design Verification Engineer role based in Hyderabad. The engineer will develop and execute verification plans, create and review testbenches, and perform functional and formal verification of complex RTL designs. Daily responsibilities include writing verification test cases, running simulations, analyzing coverage results, and debugging design and testbench issues. The role involves close collaboration with design, architecture, and validation teams to ensure robust verification quality and timely sign-off. The engineer will also contribute to improving verification methodologies, automation, and best practices across projects.
Qualifications
Exp
Job Posting Skill Set
4–6 Years
DFT Verification, Scan Chains, ATPG, Test Control Logic, JTAG, TAP Controller, Boundary Scan, Simulation
5–8 Years
SystemVerilog, UVM, IP Verification, Subsystem Verification, Testbench Development, Functional
Verification
5–8 Years
Pre-Silicon RTL Verification, Verilog, SystemVerilog, UVM, JTAG, Functional Verification
4–8 Years : ARM, Microprocessor Verification, ISA, Cache, Cache Coherency, AXI, ACE, SoC Verification,
UVM
4–8 Years
SystemVerilog, UVM, Digital Design, Power-Aware Verification, GLS, IESNLP
4–8 Years : AMBA, AXI, Bus Interconnect, Performance Verification, UPF, Python, Perl, SystemVerilog,
UVM
4–6 Years
CPU Verification, GPU Verification, SoC Verification, SystemVerilog, UVM
5–8 Years
Verilog, SystemVerilog, UVM, AMBA, AXI, AHB, RTL Verification
3–5 Years
SystemVerilog, UVM, Testbench Development, Perl, Python, Functional Verification
6–12 Years
SystemVerilog, UVM, SoC Verification, RTL Verification, Functional Verification
4–6 Years
C, C++, Processor Verification, x86, ARM, Embedded Systems, SoC Verification
4–8 Years
DFX, Design for Test, Silicon Validation, RTL Verification, SystemVerilog, UVM
5–8 Years
Ethernet, Ethernet Verification, SystemVerilog, UVM, Networking Protocols
5–8 Years
SoC Verification, SystemVerilog, UVM, Functional Verification, RTL Verification, IP Verification
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Role Description This is a full-time, on-site Design Verification Engineer role based in Hyderabad. The engineer will develop and execute verification plans, create and review testbenches, and perform functional and formal verification of complex RTL designs. Daily responsibilities include writing verification test cases, running simulations, analyzing coverage results, and debugging design and testbench issues. The role involves close collaboration with design, architecture, and validation teams to ensure robust verification quality and timely sign-off. The engineer will also contribute to improving verification methodologies, automation, and best practices across projects.
Qualifications
Exp
Job Posting Skill Set
4–6 Years
DFT Verification, Scan Chains, ATPG, Test Control Logic, JTAG, TAP Controller, Boundary Scan, Simulation
5–8 Years
SystemVerilog, UVM, IP Verification, Subsystem Verification, Testbench Development, Functional
Verification
5–8 Years
Pre-Silicon RTL Verification, Verilog, SystemVerilog, UVM, JTAG, Functional Verification
4–8 Years : ARM, Microprocessor Verification, ISA, Cache, Cache Coherency, AXI, ACE, SoC Verification,
UVM
4–8 Years
SystemVerilog, UVM, Digital Design, Power-Aware Verification, GLS, IESNLP
4–8 Years : AMBA, AXI, Bus Interconnect, Performance Verification, UPF, Python, Perl, SystemVerilog,
UVM
4–6 Years
CPU Verification, GPU Verification, SoC Verification, SystemVerilog, UVM
5–8 Years
Verilog, SystemVerilog, UVM, AMBA, AXI, AHB, RTL Verification
3–5 Years
SystemVerilog, UVM, Testbench Development, Perl, Python, Functional Verification
6–12 Years
SystemVerilog, UVM, SoC Verification, RTL Verification, Functional Verification
4–6 Years
C, C++, Processor Verification, x86, ARM, Embedded Systems, SoC Verification
4–8 Years
DFX, Design for Test, Silicon Validation, RTL Verification, SystemVerilog, UVM
5–8 Years
Ethernet, Ethernet Verification, SystemVerilog, UVM, Networking Protocols
5–8 Years
SoC Verification, SystemVerilog, UVM, Functional Verification, RTL Verification, IP Verification
Show more Show less