UT
Design Verification Engineer - # 26-12636
Accepting applicationsUS Tech Solutions · San Jose, CA
Contract Mid_senior AIASICEthernetPCIePerl
Posted
1d ago
Category
Verification
Experience
Mid_senior
Country
United States
Duration: 12 months Contract
Job Description:
Develop, maintain, and enhance scalable SystemVerilog/UVM-based verification environments for complex ASIC/SoC designs.
Develop and execute functional, constrained-random, directed, and stress test scenarios.
Work extensively on AXI, NoC/Crossbar, and performance verification.
Verify high-speed interfaces and subsystems such as PCIe, Ethernet, and HBM.
Develop reusable UVM components including agents, drivers, monitors, sequencers, scoreboards, and coverage models.
Analyze simulation and regression failures and perform debugging, triage, and root-cause analysis.
Drive functional/code coverage analysis and coverage closure in collaboration with the verification and design teams.
Responsibilities:
Develop and maintain regression suites and monitor regression health.
Automate verification and regression flows using Python, Perl, and Make.
Work with Amazon tools, verification flows, and methodologies.
Operate effectively in a start-up environment with limited documentation, taking ownership and driving tasks independently.
Collaborate with design, architecture, and verification teams to achieve overall verification closure.
Track verification status, issues, risks, and deliverables and communicate progress effectively.
Provide daily/weekly project updates to customers and ensure customer satisfaction.
Support the project on an urgent basis as the program is already in the execution phase.
Experience:
5-15 years of relevant experience in ASIC/SoC Design Verification or a related field.
Strong hands-on experience in SystemVerilog and UVM.
Extensive experience developing and maintaining scalable UVM testbenches.
Strong expertise in AXI protocols and AXI-based interconnects.
Hands-on experience with NoC/Crossbar verification and performance analysis.
Experience with regression, triage, debugging, functional coverage, and verification closure.
Exposure to PCIe, Ethernet, and/or HBM is highly preferred.
Strong scripting/automation experience using Python, Perl, and Make.
Experience working in complex ASIC/SoC verification environments and with large-scale regressions.
Ability to work independently in fast-paced environments with evolving requirements and limited documentation.
Strong communication skills with experience in customer-facing technical reporting.
Skillset:
SystemVerilog (SV)
UVM
AXI / AMBA protocols
NoC / Network-on-Chip
Crossbar / Interconnect
Performance Verification
PCIe
Ethernet
HBM
Regression & Failure Triage
Functional & Code Coverage
Coverage Closure
ASIC / SoC Verification
Python
Perl
Make
Simulation and waveform debugging
Verification methodology and testbench architecture
Customer communication and technical reporting
Education:
Bachelor’s degree in electrical or computer engineering or a Master's Degree in Electrical or Computer Engineering
Additional Qualifications:
Shift Hours: 8:00AM -5:00 PM EST
About US Tech Solutions:
US Tech Solutions is a global staff augmentation firm providing a wide range of talent on-demand and total workforce solutions. To know more about US Tech Solutions, please visit www.ustechsolutions.com.
US Tech Solutions is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, colour, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.
AI Statement: By applying, you acknowledge that AI-assisted tools may be used during hiring.
IND01
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Job Description:
Develop, maintain, and enhance scalable SystemVerilog/UVM-based verification environments for complex ASIC/SoC designs.
Develop and execute functional, constrained-random, directed, and stress test scenarios.
Work extensively on AXI, NoC/Crossbar, and performance verification.
Verify high-speed interfaces and subsystems such as PCIe, Ethernet, and HBM.
Develop reusable UVM components including agents, drivers, monitors, sequencers, scoreboards, and coverage models.
Analyze simulation and regression failures and perform debugging, triage, and root-cause analysis.
Drive functional/code coverage analysis and coverage closure in collaboration with the verification and design teams.
Responsibilities:
Develop and maintain regression suites and monitor regression health.
Automate verification and regression flows using Python, Perl, and Make.
Work with Amazon tools, verification flows, and methodologies.
Operate effectively in a start-up environment with limited documentation, taking ownership and driving tasks independently.
Collaborate with design, architecture, and verification teams to achieve overall verification closure.
Track verification status, issues, risks, and deliverables and communicate progress effectively.
Provide daily/weekly project updates to customers and ensure customer satisfaction.
Support the project on an urgent basis as the program is already in the execution phase.
Experience:
5-15 years of relevant experience in ASIC/SoC Design Verification or a related field.
Strong hands-on experience in SystemVerilog and UVM.
Extensive experience developing and maintaining scalable UVM testbenches.
Strong expertise in AXI protocols and AXI-based interconnects.
Hands-on experience with NoC/Crossbar verification and performance analysis.
Experience with regression, triage, debugging, functional coverage, and verification closure.
Exposure to PCIe, Ethernet, and/or HBM is highly preferred.
Strong scripting/automation experience using Python, Perl, and Make.
Experience working in complex ASIC/SoC verification environments and with large-scale regressions.
Ability to work independently in fast-paced environments with evolving requirements and limited documentation.
Strong communication skills with experience in customer-facing technical reporting.
Skillset:
SystemVerilog (SV)
UVM
AXI / AMBA protocols
NoC / Network-on-Chip
Crossbar / Interconnect
Performance Verification
PCIe
Ethernet
HBM
Regression & Failure Triage
Functional & Code Coverage
Coverage Closure
ASIC / SoC Verification
Python
Perl
Make
Simulation and waveform debugging
Verification methodology and testbench architecture
Customer communication and technical reporting
Education:
Bachelor’s degree in electrical or computer engineering or a Master's Degree in Electrical or Computer Engineering
Additional Qualifications:
Shift Hours: 8:00AM -5:00 PM EST
About US Tech Solutions:
US Tech Solutions is a global staff augmentation firm providing a wide range of talent on-demand and total workforce solutions. To know more about US Tech Solutions, please visit www.ustechsolutions.com.
US Tech Solutions is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, colour, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.
AI Statement: By applying, you acknowledge that AI-assisted tools may be used during hiring.
IND01
Show more Show less