S
Design Verification Architect
Accepting applicationsSilergy · Raleigh-Durham-Chapel Hill Area
Full-Time Mid_senior AIARMCadenceMentorPerl
Posted
3d ago
Category
Verification
Experience
Mid_senior
Country
United States
As Silergy accelerates its global expansion, we are establishing a premier US-based High-Performance Computing & Edge AI Power Center in North Carolina. With the flexibility to build and scale your team, you will be joining an elite global team of innovators committed to a multi-year, strategic offensive into the most demanding power delivery markets on the planet.
While our established teams in China continue to dominate the high-speed consumer and industrial sectors, this new US-based Center of Excellence is tasked with a singular mission: defining the next generation of power architectures for Tier-1 AI Datacenters and Edge AI platforms.
We are not just building components; we are engineering the 1,000A+ power delivery networks and ultra-efficient power architectures that will fuel the AI revolution. If you are a senior verification engineer or architect looking for the opportunity to shape verification strategy, build infrastructure from the ground up, mentor engineers and leave a lasting architectural legacy, this is an opportunity to make a significant impact.
The Mission
We are looking for a Power IC Verification Architect / Technical Lead to take technical ownership of verification architecture for complex mixed-signal power management ICs.
This is not an execution-focused verification role. The successful candidate will be responsible for architecting and establishing sophisticated UVM-based verification environments from the ground up, defining verification methodology and driving the verification strategy across complex power IC projects.
You will work closely with analog, digital, firmware, and system architects to develop robust verification environments spanning UVM, AMS, DMS and behavioural modelling. You will also provide technical leadership and mentorship as the North Carolina verification organisation continues to grow.
The ideal candidate has demonstrated experience building multiple verification environments from scratch and possesses the architectural depth to understand the verification flow from system-level requirements through to block-level implementation, regression and coverage closure.
Core Responsibilities
Verification Architecture
Architect and own project-level verification environments for complex mixed-signal and power management ICs.
Build sophisticated UVM environments from scratch, including the overall testbench architecture, components, stimulus generation, score boarding, coverage and regression infrastructure.
Define verification methodologies and architectures that can scale across multiple power IC projects.
Establish verification strategies spanning block, subsystem and full-chip levels.
Drive verification architecture decisions from initial project definition through tape-out and coverage closure.
UVM & SystemVerilog
Develop and maintain advanced, coverage-driven UVM environments using SystemVerilog and object-oriented verification methodologies.
Define reusable verification components and infrastructure that can be leveraged across multiple products.
Develop constrained-random stimulus, functional coverage, assertions, scoreboards, monitors, drivers and protocol checkers.
Establish robust regression strategies and debug methodologies.
Lead the technical resolution of complex verification issues across analog and digital domains.
Firmware & Hardware/Software Integration
Integrate embedded firmware into UVM-based verification environments.
Develop verification strategies for firmware/hardware interaction prior to silicon.
Work with embedded processors and ARM-based architectures where applicable.
Understand how firmware interacts with digital RTL, analog behavioural models and power-management functions.
Develop co-simulation and verification environments capable of validating hardware/firmware interaction.
Power IC Verification
Apply verification expertise to power management ICs, including DC/DC converters, multi-phase controllers, power sequencing, protection circuits and related power-management functions.
Work closely with power IC designers to understand circuit behaviour, operating modes, corner cases and failure mechanisms.
Use power IC knowledge to develop meaningful verification strategies rather than simply applying generic digital verification methodologies.
Technical Leadership & Mentorship
Act as a senior technical authority within the verification organisation.
Mentor and develop junior and mid-level verification engineers.
Establish best practices, methodologies and reusable verification infrastructure.
Help shape the growth and technical direction of the North Carolina verification team.
Work closely with engineering leadership to define future verification capabilities and hiring requirements.
What You Bring
Essential
10+ years of relevant semiconductor verification experience, or equivalent depth of technical experience.
Senior Staff, Principal, Architect or Technical Lead-level experience.
Demonstrated ability to architect and build multiple UVM verification environments from scratch.
Deep expertise in SystemVerilog and UVM.
Strong understanding of verification architecture from test planning through to coverage closure.
Experience working across complex mixed-signal semiconductor projects.
Experience with AMS and/or DMS verification methodologies.
Experience integrating or verifying firmware within a hardware/UVM environment.
Ability to understand embedded/ARM-based architectures and hardware/firmware interaction.
Strong communication and technical leadership skills.
Preferred
Experience verifying Power Management ICs, DC/DC converters, multi-phase controllers, or related power-management architectures.
Experience with mixed-signal verification within a major semiconductor company.
Experience with Cadence Xcelium, Virtuoso, Spectre, Maestro, AMS Designer, or equivalent verification environments.
Experience with DMS and RNM methodologies.
Experience developing reusable verification frameworks and methodologies across multiple projects.
Python, Perl, TCL, Makefile or other scripting/automation experience.
Experience mentoring and technically leading verification engineers.
What We're Looking For
The key differentiator for this position is architectural ownership.
We are not looking for someone who has primarily operated within an established UVM environment. We need an engineer who can explain, demonstrate and defend how they have designed and implemented verification environments from the ground up.
You should be able to demonstrate:
Multiple UVM environments personally architected from scratch.
Ownership of verification architecture rather than simply test development.
Strong understanding of the interaction between digital RTL, analog models and firmware.
Experience establishing verification methodology and infrastructure.
The technical maturity to mentor other engineers and act as the verification authority for complex projects.
Show more Show less
While our established teams in China continue to dominate the high-speed consumer and industrial sectors, this new US-based Center of Excellence is tasked with a singular mission: defining the next generation of power architectures for Tier-1 AI Datacenters and Edge AI platforms.
We are not just building components; we are engineering the 1,000A+ power delivery networks and ultra-efficient power architectures that will fuel the AI revolution. If you are a senior verification engineer or architect looking for the opportunity to shape verification strategy, build infrastructure from the ground up, mentor engineers and leave a lasting architectural legacy, this is an opportunity to make a significant impact.
The Mission
We are looking for a Power IC Verification Architect / Technical Lead to take technical ownership of verification architecture for complex mixed-signal power management ICs.
This is not an execution-focused verification role. The successful candidate will be responsible for architecting and establishing sophisticated UVM-based verification environments from the ground up, defining verification methodology and driving the verification strategy across complex power IC projects.
You will work closely with analog, digital, firmware, and system architects to develop robust verification environments spanning UVM, AMS, DMS and behavioural modelling. You will also provide technical leadership and mentorship as the North Carolina verification organisation continues to grow.
The ideal candidate has demonstrated experience building multiple verification environments from scratch and possesses the architectural depth to understand the verification flow from system-level requirements through to block-level implementation, regression and coverage closure.
Core Responsibilities
Verification Architecture
Architect and own project-level verification environments for complex mixed-signal and power management ICs.
Build sophisticated UVM environments from scratch, including the overall testbench architecture, components, stimulus generation, score boarding, coverage and regression infrastructure.
Define verification methodologies and architectures that can scale across multiple power IC projects.
Establish verification strategies spanning block, subsystem and full-chip levels.
Drive verification architecture decisions from initial project definition through tape-out and coverage closure.
UVM & SystemVerilog
Develop and maintain advanced, coverage-driven UVM environments using SystemVerilog and object-oriented verification methodologies.
Define reusable verification components and infrastructure that can be leveraged across multiple products.
Develop constrained-random stimulus, functional coverage, assertions, scoreboards, monitors, drivers and protocol checkers.
Establish robust regression strategies and debug methodologies.
Lead the technical resolution of complex verification issues across analog and digital domains.
Firmware & Hardware/Software Integration
Integrate embedded firmware into UVM-based verification environments.
Develop verification strategies for firmware/hardware interaction prior to silicon.
Work with embedded processors and ARM-based architectures where applicable.
Understand how firmware interacts with digital RTL, analog behavioural models and power-management functions.
Develop co-simulation and verification environments capable of validating hardware/firmware interaction.
Power IC Verification
Apply verification expertise to power management ICs, including DC/DC converters, multi-phase controllers, power sequencing, protection circuits and related power-management functions.
Work closely with power IC designers to understand circuit behaviour, operating modes, corner cases and failure mechanisms.
Use power IC knowledge to develop meaningful verification strategies rather than simply applying generic digital verification methodologies.
Technical Leadership & Mentorship
Act as a senior technical authority within the verification organisation.
Mentor and develop junior and mid-level verification engineers.
Establish best practices, methodologies and reusable verification infrastructure.
Help shape the growth and technical direction of the North Carolina verification team.
Work closely with engineering leadership to define future verification capabilities and hiring requirements.
What You Bring
Essential
10+ years of relevant semiconductor verification experience, or equivalent depth of technical experience.
Senior Staff, Principal, Architect or Technical Lead-level experience.
Demonstrated ability to architect and build multiple UVM verification environments from scratch.
Deep expertise in SystemVerilog and UVM.
Strong understanding of verification architecture from test planning through to coverage closure.
Experience working across complex mixed-signal semiconductor projects.
Experience with AMS and/or DMS verification methodologies.
Experience integrating or verifying firmware within a hardware/UVM environment.
Ability to understand embedded/ARM-based architectures and hardware/firmware interaction.
Strong communication and technical leadership skills.
Preferred
Experience verifying Power Management ICs, DC/DC converters, multi-phase controllers, or related power-management architectures.
Experience with mixed-signal verification within a major semiconductor company.
Experience with Cadence Xcelium, Virtuoso, Spectre, Maestro, AMS Designer, or equivalent verification environments.
Experience with DMS and RNM methodologies.
Experience developing reusable verification frameworks and methodologies across multiple projects.
Python, Perl, TCL, Makefile or other scripting/automation experience.
Experience mentoring and technically leading verification engineers.
What We're Looking For
The key differentiator for this position is architectural ownership.
We are not looking for someone who has primarily operated within an established UVM environment. We need an engineer who can explain, demonstrate and defend how they have designed and implemented verification environments from the ground up.
You should be able to demonstrate:
Multiple UVM environments personally architected from scratch.
Ownership of verification architecture rather than simply test development.
Strong understanding of the interaction between digital RTL, analog models and firmware.
Experience establishing verification methodology and infrastructure.
The technical maturity to mentor other engineers and act as the verification authority for complex projects.
Show more Show less