Design of Test Engineer

Company Description
Pi Square Technologies is a leading provider of Automotive and IT technology solutions, headquartered in Farmington Hills, Michigan, with global delivery centers in Hyderabad and Bangalore, India. The company collaborates with major OEMs and Tier 1 suppliers in the automotive industry to provide state-of-the-art embedded software development, training, and consulting. Known for driving innovation in digital transformation, Pi Square Technologies specializes in enterprise software solutions, AI/ML, SAP, and D365 cloud services, supporting clients to achieve their business goals. With a commitment to diversity and inclusion, Pi Square aims to build collaborative teams that represent the communities they serve while advancing technology to enhance the future.

Role Description
We are seeking a skilled Design For Test Engineer for a full-time position based in Santa Clara, CA. The role involves developing, implementing, and validating Design for Testability (DFT) strategies for integrated circuits. The engineer will collaborate with cross-functional teams to design, optimize, and verify test plans, analyze test data, and help identify potential design and manufacturing issues. Additional responsibilities include generating technical documentation, ensuring compliance with industry standards, and actively contributing to process improvements. This is an onsite role, requiring a proactive individual with strong problem-solving abilities and technical knowledge.

Qualifications
5+ years of hands-on experience in DFT and ATPG for SoC or ASIC designs
Strong understanding of DFT fundamentals including controllability, observability, and scan-based testing
Proven expertise in ATPG pattern generation, analysis, and debug
Experience with MBIST, including memory test architectures and diagnostics
Knowledge of IO Test methodologies for interface and pin level validation
Solid understanding of clock DFT and clock verification concepts
Strong grasp of digital design and RTL fundamentals
Experience with industry standard DFT/ATPG EDA tools
Ability to work effectively in fast paced, high performance semiconductor programs
Strong analytical, problem solving, and communication skills
Additional Details :
Familiarity with the Siemens suite of DFT tools
DFT insertion for SCAN (with SSN) and MBIST
MBIST Repair Implementation and Verification
Generating collaterals for Test Timing and Place and Route
Expertise in IJTAG 1687 standard and good at understanding ICL and PDL standard Spec
Verification of DFT features including
Boundary Scan
JTAG
SCAN
MBIST
High Speed IO
ATPG
DRC debug
Coverage Analysis
Pattern Generation for different fault models

Please reach / share your resume to vineelkumar.p@pisquaretech.com
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