AD
Design For Testability Lead
Accepting applicationsACL Digital · Bengaluru South, Karnataka, India
Full-Time Mid_senior ATPGBISTDFTJTAGRTL
Estimated market salary
₹44-79 LPA
This is a SiliconBoard market estimate, not an employer-posted salary.
Posted
3d ago
Category
Test
Experience
Mid_senior
Country
India
Company Description ACL Digital is a design-led leader in Digital Experience, Product Innovation, Solutions, and Consulting, supporting organizations from strategy through implementation and ongoing management. The company focuses on customer journeys and design to help large enterprises, SMBs, and start-ups accelerate innovation and business transformation. As a pioneer in delivering business innovation, integration, and transformation through disruptive technologies, ACL Digital offers clients competitive advantage and fresh perspectives on complex challenges. With a multicultural and transnational workforce and as part of the ALTEN Group, which has over 50,000 employees across more than 30 countries, ACL Digital fosters a collaborative, knowledge-building environment that values diverse talent and ideas.
Role Description The Design For Testability (DFT) Lead is a full-time, on-site role based in Bengaluru South. This role is responsible for defining and implementing DFT strategies for complex digital and mixed-signal designs, ensuring robust test coverage and high product quality. The DFT Lead will collaborate closely with design, verification, and manufacturing test teams to architect scan, BIST, boundary scan, and other test structures, and to integrate them into the overall chip design flow. Day-to-day responsibilities include reviewing design specifications, driving DFT insertion and optimization, analyzing test results, debugging testability issues, and preparing documentation and guidelines for cross-functional stakeholders. The person in this role will also mentor junior engineers, contribute to methodology improvements, and support test planning and execution throughout the product lifecycle.
Qualifications
Strong expertise in DFT methodologies, including scan insertion, ATPG, boundary scan (JTAG), and built-in self-test (BIST) for digital and mixed-signal designs.
Hands-on experience with EDA tools and flows commonly used for DFT implementation, verification, and pattern generation.
Solid understanding of digital design principles, RTL design, synthesis, timing, and integration of test structures into complex SoCs or ASICs.
Proficiency in debugging test coverage gaps, yield issues, and test failures, and collaborating with design and test engineering teams to resolve them.
Ability to develop and document DFT guidelines, best practices, and reusable methodologies, and to coach and mentor engineering team members.
Excellent analytical, problem-solving, and communication skills, with the ability to work effectively in cross-functional, multicultural teams.
Bachelor’s or Master’s degree in Electrical Engineering, Electronics, or a related field, or equivalent practical experience.
Experience in semiconductor product development, from design through manufacturing test, and familiarity with industry standards and quality practices.
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Role Description The Design For Testability (DFT) Lead is a full-time, on-site role based in Bengaluru South. This role is responsible for defining and implementing DFT strategies for complex digital and mixed-signal designs, ensuring robust test coverage and high product quality. The DFT Lead will collaborate closely with design, verification, and manufacturing test teams to architect scan, BIST, boundary scan, and other test structures, and to integrate them into the overall chip design flow. Day-to-day responsibilities include reviewing design specifications, driving DFT insertion and optimization, analyzing test results, debugging testability issues, and preparing documentation and guidelines for cross-functional stakeholders. The person in this role will also mentor junior engineers, contribute to methodology improvements, and support test planning and execution throughout the product lifecycle.
Qualifications
Strong expertise in DFT methodologies, including scan insertion, ATPG, boundary scan (JTAG), and built-in self-test (BIST) for digital and mixed-signal designs.
Hands-on experience with EDA tools and flows commonly used for DFT implementation, verification, and pattern generation.
Solid understanding of digital design principles, RTL design, synthesis, timing, and integration of test structures into complex SoCs or ASICs.
Proficiency in debugging test coverage gaps, yield issues, and test failures, and collaborating with design and test engineering teams to resolve them.
Ability to develop and document DFT guidelines, best practices, and reusable methodologies, and to coach and mentor engineering team members.
Excellent analytical, problem-solving, and communication skills, with the ability to work effectively in cross-functional, multicultural teams.
Bachelor’s or Master’s degree in Electrical Engineering, Electronics, or a related field, or equivalent practical experience.
Experience in semiconductor product development, from design through manufacturing test, and familiarity with industry standards and quality practices.
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