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Design for Test (DFT) - Chip Design
Accepting applicationsIntellectt Inc · Santa Clara County, CA
Full-Time Mid_senior ASICATEATPGBoundary ScanDFT
Posted
2d ago
Category
Test
Experience
Mid_senior
Country
United States
DFT Engineer – Role Clarification
📍 Location: Santa Clara, CA – Onsite
💼 Job Type: Full-Time
💰 Salary: $100K–$120K/Year (Negotiable)
🔹 Domain: Semiconductor / VLSI – ASIC/SoC Chip Design
This is a chip design-side DFT (Design for Testability) engineering role, not a traditional semiconductor/chip testing or ATE testing position.
The selected candidate will work as part of the ASIC/SoC design team, responsible for implementing and verifying testability features within the chip. The role focuses on DFT/DFx implementation, SCAN, MBIST, MBIST Repair, IJTAG (IEEE 1687), JTAG, Boundary Scan, and DFT verification using tools such as Siemens Tessent.
Ideal Candidate Background
DFT / DFx Engineer
DFT Design or Implementation Engineer
DFT Verification Engineer
ASIC/SoC DFT Engineer
Siemens Tessent / DFT Tools experience
SCAN / SSN
MBIST & MBIST Repair
IJTAG / IEEE 1687
ICL / PDL
JTAG / Boundary Scan
Important: This is not primarily an ATE, production test, or semiconductor test engineering role. Candidates should have hands-on DFT experience within the chip design flow.
Also, ATPG experience is not mandatory for this requirement.
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📍 Location: Santa Clara, CA – Onsite
💼 Job Type: Full-Time
💰 Salary: $100K–$120K/Year (Negotiable)
🔹 Domain: Semiconductor / VLSI – ASIC/SoC Chip Design
This is a chip design-side DFT (Design for Testability) engineering role, not a traditional semiconductor/chip testing or ATE testing position.
The selected candidate will work as part of the ASIC/SoC design team, responsible for implementing and verifying testability features within the chip. The role focuses on DFT/DFx implementation, SCAN, MBIST, MBIST Repair, IJTAG (IEEE 1687), JTAG, Boundary Scan, and DFT verification using tools such as Siemens Tessent.
Ideal Candidate Background
DFT / DFx Engineer
DFT Design or Implementation Engineer
DFT Verification Engineer
ASIC/SoC DFT Engineer
Siemens Tessent / DFT Tools experience
SCAN / SSN
MBIST & MBIST Repair
IJTAG / IEEE 1687
ICL / PDL
JTAG / Boundary Scan
Important: This is not primarily an ATE, production test, or semiconductor test engineering role. Candidates should have hands-on DFT experience within the chip design flow.
Also, ATPG experience is not mandatory for this requirement.
Show more Show less