C
Design Engineer II
Accepting applicationsCadence · Bengaluru, Karnataka, India
Full-Time Associate C++CadenceDDRFPGAPCIe
Posted
4d ago
Category
Design
Experience
Associate
Country
India
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Minimum Qualifications
2-4 years (with Btech) or 1-2 years (with Mtech) of experience in Post-Silicon Physical Layer Electrical Validation
Deep Physical Layer electrical validation experience on AT LEAST ONE High speed SERDES protocol like PCIe, USB, DP, ethernet, SRIO, JESD204, DDRIO etc
Strong hands on Experience in using lab equipment such as Oscilloscopes, Network Analyzer, Bit Error Rate Tester (BERT) etc
Preferred Qualifications
Experience managing small teams (at least 2 members and above)
Experience leading the complete post silicon validation efforts for at least one full project
1-2 years of experience in FPGA Design, PCB schematic and layout design & Prototyping
Pre-Silicon IP/SoC Physical Layer Electrical Validation experience related to board bring-up & Debug.
Familiarity with Verilog RTL coding, FPGA coding, Labview, python, C/C++, TCL
Experience conducting hiring interviews and mentoring new hires
BE/BTech/ME/MTech or equivalent
We’re doing work that matters. Help us solve what others can’t.
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Minimum Qualifications
2-4 years (with Btech) or 1-2 years (with Mtech) of experience in Post-Silicon Physical Layer Electrical Validation
Deep Physical Layer electrical validation experience on AT LEAST ONE High speed SERDES protocol like PCIe, USB, DP, ethernet, SRIO, JESD204, DDRIO etc
Strong hands on Experience in using lab equipment such as Oscilloscopes, Network Analyzer, Bit Error Rate Tester (BERT) etc
Preferred Qualifications
Experience managing small teams (at least 2 members and above)
Experience leading the complete post silicon validation efforts for at least one full project
1-2 years of experience in FPGA Design, PCB schematic and layout design & Prototyping
Pre-Silicon IP/SoC Physical Layer Electrical Validation experience related to board bring-up & Debug.
Familiarity with Verilog RTL coding, FPGA coding, Labview, python, C/C++, TCL
Experience conducting hiring interviews and mentoring new hires
BE/BTech/ME/MTech or equivalent
We’re doing work that matters. Help us solve what others can’t.
Show more Show less