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Design Engineer
Accepting applicationsYochana · Sunnyvale, CA
Full-Time Mid_senior PythonRTLSystemVerilogUVM
Posted
1d ago
Category
Verification
Experience
Mid_senior
Country
United States
Job Role: Design Engineer III
Location: Sunnyvale, CA (Day1 Onsite)
Mode: Fulltime
Job Description:
About the role: Design Verification einfngineer for wearables silicon accelerator IPs — testbench development, coverage-driven verification, RTL debug, and power/performance measurement.
Top 3 Must-Have Skills:
SystemVerilog / UVM testbench development.
Functional coverage + assertion-based verification and coverage closure.
RTL debug (VCS/Xcelium) + Python automation; power/perf measurement.
Previous Meta experience preferred.
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Location: Sunnyvale, CA (Day1 Onsite)
Mode: Fulltime
Job Description:
About the role: Design Verification einfngineer for wearables silicon accelerator IPs — testbench development, coverage-driven verification, RTL debug, and power/performance measurement.
Top 3 Must-Have Skills:
SystemVerilog / UVM testbench development.
Functional coverage + assertion-based verification and coverage closure.
RTL debug (VCS/Xcelium) + Python automation; power/perf measurement.
Previous Meta experience preferred.
Show more Show less