B
Design Engineer
Accepting applicationsBroadcom · Bengaluru, Karnataka, India
Full-Time Mid_senior AIASICEthernetPerlPython
Posted
1d ago
Category
Design
Experience
Mid_senior
Country
India
Job Description:
Broadcom Core Switching Group is an industry leader in developing complex and cutting-edge Ethernet Switching ASIC's and drives the innovation needed for AI & DC infrastructure. We are looking for a motivated individual to join our team as an RTL Design Engineer/micro-architect to work on the next generation of networking and security protocols
Your job role will include the following tasks:
Architect block level design specifications from the system/marketing requirements
Efficient design implementation for different components of networking ASICs.
RTL coding, Lint & CDC checks, Logic Synthesis and driving Timing/Area/Power optimizations in latest technology nodes
Support pre & post silicon verification activities, including the usage of SVAs/Formal technologies for verification closure
Support external teams for IP integration, physical implementation with relevant documentation
The successful candidate will satisfy the below requirements:
B.S degree in EE with 12 years of work experience or Masters in EE with 8 years of work experience in Front End Logic Design
Experience with HDLs such as Verilog/System-Verilog and scripting languages such as Perl/TCL/Python
Experience with Ethernet L2/L3/L4 networking protocols and/or Security protocols/algorithms is strongly preferred
High Speed Digital Design with logic pipelining for 1Ghz+ clock rates
Exposure to area/power estimation methods and Code Assist tools is desirable
Problem-solving attitude with strong analytical, verbal and written communication skills
R026291
Show more Show less
Broadcom Core Switching Group is an industry leader in developing complex and cutting-edge Ethernet Switching ASIC's and drives the innovation needed for AI & DC infrastructure. We are looking for a motivated individual to join our team as an RTL Design Engineer/micro-architect to work on the next generation of networking and security protocols
Your job role will include the following tasks:
Architect block level design specifications from the system/marketing requirements
Efficient design implementation for different components of networking ASICs.
RTL coding, Lint & CDC checks, Logic Synthesis and driving Timing/Area/Power optimizations in latest technology nodes
Support pre & post silicon verification activities, including the usage of SVAs/Formal technologies for verification closure
Support external teams for IP integration, physical implementation with relevant documentation
The successful candidate will satisfy the below requirements:
B.S degree in EE with 12 years of work experience or Masters in EE with 8 years of work experience in Front End Logic Design
Experience with HDLs such as Verilog/System-Verilog and scripting languages such as Perl/TCL/Python
Experience with Ethernet L2/L3/L4 networking protocols and/or Security protocols/algorithms is strongly preferred
High Speed Digital Design with logic pipelining for 1Ghz+ clock rates
Exposure to area/power estimation methods and Code Assist tools is desirable
Problem-solving attitude with strong analytical, verbal and written communication skills
R026291
Show more Show less
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