AT
Design Engineer
Accepting applicationsAcceler8 Talent · Berkeley, CA
Full-Time Mid_senior AIRTLSPISystemVerilogVerilog
Posted
3d ago
Category
Design
Experience
Mid_senior
Country
United States
Hiring: Digital IC Design Engineer
Location: Berkeley, California
Working model: Onsite, five days per week
Compensation: From $180,000 base salary, plus equity
Visa sponsorship: Available
We are hiring a Digital IC Design Engineer to join an early-stage photonic computing company building a new hardware platform for AI workloads. This is a broad, hands-on role for someone who wants to take digital blocks from RTL design through synthesis, physical implementation, tape-out and silicon bring-up.
What you will own
Design and integrate RTL for digital functions and interfaces, including UART, SPI and SRAM connectivity.
Run synthesis, static timing analysis, gate-level simulation and place-and-route flows.
Work with advanced process technologies, standard-cell libraries and physical-design constraints.
Support chip tape-out, lab bring-up and post-silicon validation.
Work across architecture, design, verification and implementation as needed.
Help build the company’s wider digital IC capability as the team grows.
What we are looking for
Strong RTL experience using Verilog or SystemVerilog.
Hands-on exposure to synthesis, timing analysis and physical implementation.
Experience taking a chip or substantial digital block through implementation and into the lab.
Comfort working across multiple stages of the digital design flow.
A resourceful, ownership-driven approach suited to an early-stage startup.
Why join?
This is an opportunity to own meaningful parts of a chip, work across photonic ICs, electronic ICs, packaging and architecture, and help shape a new computing platform from an early stage.
Show more Show less
Location: Berkeley, California
Working model: Onsite, five days per week
Compensation: From $180,000 base salary, plus equity
Visa sponsorship: Available
We are hiring a Digital IC Design Engineer to join an early-stage photonic computing company building a new hardware platform for AI workloads. This is a broad, hands-on role for someone who wants to take digital blocks from RTL design through synthesis, physical implementation, tape-out and silicon bring-up.
What you will own
Design and integrate RTL for digital functions and interfaces, including UART, SPI and SRAM connectivity.
Run synthesis, static timing analysis, gate-level simulation and place-and-route flows.
Work with advanced process technologies, standard-cell libraries and physical-design constraints.
Support chip tape-out, lab bring-up and post-silicon validation.
Work across architecture, design, verification and implementation as needed.
Help build the company’s wider digital IC capability as the team grows.
What we are looking for
Strong RTL experience using Verilog or SystemVerilog.
Hands-on exposure to synthesis, timing analysis and physical implementation.
Experience taking a chip or substantial digital block through implementation and into the lab.
Comfort working across multiple stages of the digital design flow.
A resourceful, ownership-driven approach suited to an early-stage startup.
Why join?
This is an opportunity to own meaningful parts of a chip, work across photonic ICs, electronic ICs, packaging and architecture, and help shape a new computing platform from an early stage.
Show more Show less