II
DDR Design Verification Engineer
Accepting applicationsInterSources Inc · San Jose, CA
Full-Time Executive DDRSoCUVMaiperl
Posted
6d ago
Category
Verification
Experience
Executive
Country
United States
BS in Computer Science/EE with 10+ years of experience or MS in computer science/EE with 8+ years of experience in SoC design verification.
Experience with block level, cluster level or chip/SoC level verification.
Proficiency in system verilog, UVM, constrained random and coverage driven verification methodology.
DDR controller and/or DDR-IO verification experience is a must.
Very good understanding of LPDDR JDEC specifications preferably for LPDDR5.
Good understanding of DDR controller and phy functionality.
Experience with development of test bench components, test plans for DDR/LPDDR IP verification.
Good system verilog programming, debug and problem solving skills.
Scripting languages, python or perl is a plus
Show more Show less
Experience with block level, cluster level or chip/SoC level verification.
Proficiency in system verilog, UVM, constrained random and coverage driven verification methodology.
DDR controller and/or DDR-IO verification experience is a must.
Very good understanding of LPDDR JDEC specifications preferably for LPDDR5.
Good understanding of DDR controller and phy functionality.
Experience with development of test bench components, test plans for DDR/LPDDR IP verification.
Good system verilog programming, debug and problem solving skills.
Scripting languages, python or perl is a plus
Show more Show less