CPU-RTL design Engineer

Key Responsibilities:
Strong experience in CPU Core RTL Design: Single-thread / Multi-thread, In-order / Limited Out-of-Order pipelines
Must have completed at least one full CPU core development cycle
Experience in real-time/high-performance cores (e.g., ARM Cortex-R52 or equivalent)
Hands-on in RTL coding (Verilog/SystemVerilog), Timing analysis & closure, Power analysis & optimization
Good understanding of: CPU pipeline and Performance, PPA trade-offs
Ability to debug and fix timing/power issues and collaborate with PD/Verification teams


Interested can share cv to Karthick.Viswa@smartsocs.com
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