CA
CPU & Processor Subsystems-Senior Design Verification Engineer
Accepting applicationsCore ASIC Inc · Greater Bengaluru Area
Full-Time Mid_senior ASICRTLSoCSystemVerilogUVM
Estimated market salary
₹28-51 LPA
This is a SiliconBoard market estimate, not an employer-posted salary.
Posted
3d ago
Category
Verification
Experience
Mid_senior
Country
India
Job Title: Senior Design Verification Engineer – CPU & Processor Subsystems
Company: CoreASIC Technologies Private Limited
Location: Hyderabad, India (Hybrid / On-site)
Job Type: Full-Time
Experience Level: 4+ Years
About Core ASIC
Core ASIC is a rapidly growing semiconductor services provider driving high-performance silicon engineering across advanced tech domains. We deliver robust, first-pass silicon verification solutions for world-class product design clients. To accelerate our custom processor verification programs, we are looking for a highly skilled and analytical Senior DV Engineer (CPU/Subsystem Verification) to join our technical execution team in Hyderabad.
Role Summary
In this role, you will lead and execute the pre-silicon functional verification of high-performance CPU cores, multi-core cache coherent subsystems, or custom processor pipelines. Leveraging SystemVerilog and UVM, you will own the development of advanced testbench environments, build robust scoreboards for data integrity checking, and drive rigorous coverage metrics to hit tight tape-out timelines. This position requires deep analytical thinking for systematic RTL debug and root-cause analysis.
Key Responsibilities
Testbench Architecture & Infrastructure: Develop, optimize, and maintain modular, reusable block and subsystem-level verification environments using SystemVerilog and UVM.
CPU Subsystem Verification: Write exhaustive verification plans by analyzing microarchitectural specs of CPU/processor blocks, pipeline stages, cache structures, or memory management subsystems.
Scoreboarding & Checker Logic: Implement complex self-checking mechanisms, predictor models, and end-to-end scoreboards to validate data routing, register transactions, and instruction-set architecture (ISA) execution.
Coverage Closure: Design, implement, and track functional coverage models, cross-coverage groups, and assertions (SVA) to identify coverage holes and systematically push for 100% code and functional closure.
Debug & Root-Cause Analysis: Execute intensive debugging on failing regression suites using modern tools (e.g., Verdi, VCS) to precisely isolate RTL bugs from testbench infra issues.
Qualifications & Skills
Experience: 4+ years of dedicated experience in ASIC/SoC pre-silicon functional design verification.
Language & Methodology: Expert-level command over SystemVerilog (SV) and Universal Verification Methodology (UVM) for constrained-random verification environments.
Processor Domain Knowledge: Solid understanding of computer architecture principles, pipeline stalls, branch prediction mechanisms, interrupt handling, or cache coherency.
Scoreboarding & Verification Metrics: Proven track record constructing automated verification checkers and writing targeted functional coverpoints.
Debug Proficiency: Outstanding hands-on trace debug and root-cause analysis skills within simulation wave environments.
Education: B.E./B.Tech or M.E./M.Tech in Electrical/Electronics Engineering, Computer Engineering, or a related field.
What We Offer
Competitive salary package with performance incentives.
Exposure to leading edge processor/CPU sub-system architectures.
Collaborative culture with career acceleration paths in advanced VLSI domains.
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Company: CoreASIC Technologies Private Limited
Location: Hyderabad, India (Hybrid / On-site)
Job Type: Full-Time
Experience Level: 4+ Years
About Core ASIC
Core ASIC is a rapidly growing semiconductor services provider driving high-performance silicon engineering across advanced tech domains. We deliver robust, first-pass silicon verification solutions for world-class product design clients. To accelerate our custom processor verification programs, we are looking for a highly skilled and analytical Senior DV Engineer (CPU/Subsystem Verification) to join our technical execution team in Hyderabad.
Role Summary
In this role, you will lead and execute the pre-silicon functional verification of high-performance CPU cores, multi-core cache coherent subsystems, or custom processor pipelines. Leveraging SystemVerilog and UVM, you will own the development of advanced testbench environments, build robust scoreboards for data integrity checking, and drive rigorous coverage metrics to hit tight tape-out timelines. This position requires deep analytical thinking for systematic RTL debug and root-cause analysis.
Key Responsibilities
Testbench Architecture & Infrastructure: Develop, optimize, and maintain modular, reusable block and subsystem-level verification environments using SystemVerilog and UVM.
CPU Subsystem Verification: Write exhaustive verification plans by analyzing microarchitectural specs of CPU/processor blocks, pipeline stages, cache structures, or memory management subsystems.
Scoreboarding & Checker Logic: Implement complex self-checking mechanisms, predictor models, and end-to-end scoreboards to validate data routing, register transactions, and instruction-set architecture (ISA) execution.
Coverage Closure: Design, implement, and track functional coverage models, cross-coverage groups, and assertions (SVA) to identify coverage holes and systematically push for 100% code and functional closure.
Debug & Root-Cause Analysis: Execute intensive debugging on failing regression suites using modern tools (e.g., Verdi, VCS) to precisely isolate RTL bugs from testbench infra issues.
Qualifications & Skills
Experience: 4+ years of dedicated experience in ASIC/SoC pre-silicon functional design verification.
Language & Methodology: Expert-level command over SystemVerilog (SV) and Universal Verification Methodology (UVM) for constrained-random verification environments.
Processor Domain Knowledge: Solid understanding of computer architecture principles, pipeline stalls, branch prediction mechanisms, interrupt handling, or cache coherency.
Scoreboarding & Verification Metrics: Proven track record constructing automated verification checkers and writing targeted functional coverpoints.
Debug Proficiency: Outstanding hands-on trace debug and root-cause analysis skills within simulation wave environments.
Education: B.E./B.Tech or M.E./M.Tech in Electrical/Electronics Engineering, Computer Engineering, or a related field.
What We Offer
Competitive salary package with performance incentives.
Exposure to leading edge processor/CPU sub-system architectures.
Collaborative culture with career acceleration paths in advanced VLSI domains.
Show more Show less