MT
Core Logic Design Lead
Accepting applicationsMulya Technologies · Greater Hyderabad Area
Full-Time Mid_senior ARMAsicRTLSOC
Estimated market salary
₹13-24 LPA
This is a SiliconBoard market estimate, not an employer-posted salary.
Posted
3d ago
Category
Design
Experience
Mid_senior
Country
India
Core Logic Design Lead
Fortune 100 Organization
Location: Hyderabad / Bangalore
Your Role And Responsibilitie
s
Collaborate with micro architect, designers to propose and demonstrate the core CPU and Fabric micro architectural features to drive performance per area/power on targeted workload
s.Collaborate with Silicon Bringup team and Software team to verify and debug microarchitecture and its performanc
e.Strong ability to communicate and drive to closure micro architectural proposals within Cache and coherent Fabric with technical stakeholders across Chip/System with presentation and document
s.Strong collaborative and interpersonal skills and a proven ability to guide new design team membe
rs
Required Technical And Professional Expert
ise
15+ years experience in high performance microprocessor architecture, micro architecture, computer architect
ure.Deep knowledge of Processor Instruction set architecture (e.g ARM, X86, Pow
er).Deep understanding/experience of CPU microarchitecture and architecture with experience in: L1, L2 caches, Prefetch, Cache Coherent interconnect Fab
ric.Large multi chip/system Cache Coherency experience, SOC/Multi-Chip Coherency Fabric and Memory Subsystem micro-architect
ure.Deep understanding/experience of Coherent Interconnect Bus Architecture for CPU on-chip/off-chip network, MP coherency and last level system cac
hes.Strong RTL design expertise and hands-on experience of Processor/Asic design flow: design, verification, PD synthesis, ECO, bring
up.
C
onta
ctUdayMulya Techno
logiesmuday_bhaskar@yah
oo.comhttps://mulyatec
h.com/
Show more Show less
Fortune 100 Organization
Location: Hyderabad / Bangalore
Your Role And Responsibilitie
s
Collaborate with micro architect, designers to propose and demonstrate the core CPU and Fabric micro architectural features to drive performance per area/power on targeted workload
s.Collaborate with Silicon Bringup team and Software team to verify and debug microarchitecture and its performanc
e.Strong ability to communicate and drive to closure micro architectural proposals within Cache and coherent Fabric with technical stakeholders across Chip/System with presentation and document
s.Strong collaborative and interpersonal skills and a proven ability to guide new design team membe
rs
Required Technical And Professional Expert
ise
15+ years experience in high performance microprocessor architecture, micro architecture, computer architect
ure.Deep knowledge of Processor Instruction set architecture (e.g ARM, X86, Pow
er).Deep understanding/experience of CPU microarchitecture and architecture with experience in: L1, L2 caches, Prefetch, Cache Coherent interconnect Fab
ric.Large multi chip/system Cache Coherency experience, SOC/Multi-Chip Coherency Fabric and Memory Subsystem micro-architect
ure.Deep understanding/experience of Coherent Interconnect Bus Architecture for CPU on-chip/off-chip network, MP coherency and last level system cac
hes.Strong RTL design expertise and hands-on experience of Processor/Asic design flow: design, verification, PD synthesis, ECO, bring
up.
C
onta
ctUdayMulya Techno
logiesmuday_bhaskar@yah
oo.comhttps://mulyatec
h.com/
Show more Show less
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