LI
Contract Physical Design Engineer
Accepting applicationsLanceSoft, Inc. · Folsom, CA
Contract Mid_senior ASICFinFETRTLSynopsys
Posted
3d ago
Category
Design
Experience
Mid_senior
Country
United States
Job Title - Physical Design Engineer
Job Location - Folsom-CA
Job Description-
Experience: 10+ years
Key Requirements:
Strong end-to-end RTL-to-GDS flow experience:
Synthesis → Netlist → Floorplanning → Placement → CTS → Routing → Signoff
APR (Automatic Place & Route) experience is a key requirement.
3nm FinFET process experience is highly preferred/important.
Strong GDS/GDSII and STA (Static Timing Analysis) experience required.
Strong experience with Clock Tree / CTS, Timing Closure, and Signoff.
Synopsys Compiler tools are highly desirable.
Day-to-day work will primarily involve RTL blocks, Clock Tree, Timing, and Signoff activities.
Candidates should have strong hands-on ASIC Physical Design / Implementation experience.
Preferred Candidate Background:
Candidates from Broadcom, Google, Intel, etc. are highly preferred.
Preference for candidates with experience in advanced-node semiconductor projects, especially 3nm FinFET.
Duration:
Initial duration: 3 months
Potential extension: 1 additional year
Expected total duration: up to 1 year 3 months, depending on project requirements.
Top 5 Skills to Screen:
RTL-to-GDS
APR / Place & Route
3nm FinFET
STA + Timing Closure
GDS + Signoff
Show more Show less
Job Location - Folsom-CA
Job Description-
Experience: 10+ years
Key Requirements:
Strong end-to-end RTL-to-GDS flow experience:
Synthesis → Netlist → Floorplanning → Placement → CTS → Routing → Signoff
APR (Automatic Place & Route) experience is a key requirement.
3nm FinFET process experience is highly preferred/important.
Strong GDS/GDSII and STA (Static Timing Analysis) experience required.
Strong experience with Clock Tree / CTS, Timing Closure, and Signoff.
Synopsys Compiler tools are highly desirable.
Day-to-day work will primarily involve RTL blocks, Clock Tree, Timing, and Signoff activities.
Candidates should have strong hands-on ASIC Physical Design / Implementation experience.
Preferred Candidate Background:
Candidates from Broadcom, Google, Intel, etc. are highly preferred.
Preference for candidates with experience in advanced-node semiconductor projects, especially 3nm FinFET.
Duration:
Initial duration: 3 months
Potential extension: 1 additional year
Expected total duration: up to 1 year 3 months, depending on project requirements.
Top 5 Skills to Screen:
RTL-to-GDS
APR / Place & Route
3nm FinFET
STA + Timing Closure
GDS + Signoff
Show more Show less