Contract Hardware Engineer Mid.

ET_TN01
Job Title: Contract Hardware Engineer Mid.
Location: Mountain View, CA
Duration: 12 Months

This role is similar to FPGA Engineer with HAPS or Xilinx
Location: Mountain view CA (Complete Onsite)
Experience: 7 years (Relevant)
What You'll Be Doing:
Develop C and C based test content, low-level drivers and custom firmware at the subsystem and SoC levels, including self-checking tests that run on embedded processors.
Extend the compile and build flow to support custom Firmware-style tests
Serve as a technical owner for the team's FPGA prototyping platform (such as HAPS or Xilinx): create board images and bit files. Design additional custom FPGA RTL for protocol interfaces and feature enablement. Release stable platforms to the firmware team and keep them working as the design evolves.
Develop and extend custom python tooling to interface with the FPGA platform.
Debug FPGA and post-silicon issues using tools such as JTAG debuggers, logic analyzers, oscilloscopes, and multimeters.
Drive post-silicon bring-up and validation in the lab, run the validation suites on first silicon, meet bring-up exit criteria on schedule, and debug platform issues such as JTAG failures, UART connectivity, and boot failures alongside the design, firmware, hardware and security teams.
Root-cause failing post-silicon tests to closure, collecting and analyzing scan dumps for low-level issues such as boot ROM and built-in self-test bugs, coordinating cross-team debug, and delivering fixes such as handling fatal errors, correcting driver access violations, and reconciling registers modified by boot firmware.
What we are looking for:
Experience developing C and C test content for subsystem and SoC verification, including bare-metal and firmware style tests, with working knowledge of SystemVerilog testbenches.
Experience bringing up and maintaining FPGA prototyping or emulation platforms (such as HAPS or Xilinx), including board images, platform tooling, and testbench changes that enable firmware and validation teams.
Hands-on hardware debug experience with tools such as JTAG debuggers, logic analyzers, oscilloscopes, and multimeters.
Experience with post-silicon verification of IP, subsystems, or SoCs through the full cycle, including test planning, test development, failure debug, and coverage signoff.
Experience with post-silicon bring-up and validation, including running test test suites on silicon and debugging boot, platform, and connectivity issues in a lab environment.
Proficiency in Python, or a similar scripting languages such as Perl or Ruby, for test automation, build flows, and log or data parsing.
In-depth knowledge of verification principles, testbench architecture and stimulus generation, with a track record of debugging complex designs.
Experience with industry protocols such as AMBA (AXI/AHB/APB), JTAG, SPI, I2C/I3C and USB.
Experience collaborating across architecture, design, firmware, and validation teams, with strong communication skills.
Strong understanding of silicon and/or computer architecture.
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