SI
Circuit Design Engineer
Accepting applicationsSysTechCorp Inc · Hyderabad, Telangana, India
Full-Time Entry CadenceDDRFinFETPCIeSerDes
Estimated market salary
₹9-16 LPA
This is a SiliconBoard market estimate, not an employer-posted salary.
Posted
21h ago
Category
Verification
Experience
Entry
Country
India
Title: Circuit Design Engineer
Location: Bangalore
Experience: 7+ Years
Role Summary:
Design analog and high-speed circuits including Transmitter & Receiver equalization (FFE/CTLE/DFE), op-amps, Bandgap references, regulators, charge pumps, ADC, PLL, DLL, CDR and other precision blocks in advanced FinFET process nodes, preferably TSMC 3nm. Conduct simulations across PVT corners, collaborate with layout and verification teams, and ensure ESD-aware circuit design. Optimize circuits for power, performance, and area.
* Circuit architecture, schematic design for DDR & Serdes PHY IPs.
* Simulation across PVT corners and worst-case analysis
* Collaboration with layout, verification, and reliability teams
* ESD-aware circuit design and protection
* Design for manufacturability and yield enhancement
* Documentation and IP integration support
* Prior experience with Cadence ADE/Artist, Spectre, EMIR & reliability flows.
Note: Experience in High-speed Memory interfaces (DDR3/4/5, LPDDR5/6, GDDR5/6/7) or SerDes Interfaces (PCIe, MIPI, HDMI, USB, SATA etc) are mandatory for this role.
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Location: Bangalore
Experience: 7+ Years
Role Summary:
Design analog and high-speed circuits including Transmitter & Receiver equalization (FFE/CTLE/DFE), op-amps, Bandgap references, regulators, charge pumps, ADC, PLL, DLL, CDR and other precision blocks in advanced FinFET process nodes, preferably TSMC 3nm. Conduct simulations across PVT corners, collaborate with layout and verification teams, and ensure ESD-aware circuit design. Optimize circuits for power, performance, and area.
* Circuit architecture, schematic design for DDR & Serdes PHY IPs.
* Simulation across PVT corners and worst-case analysis
* Collaboration with layout, verification, and reliability teams
* ESD-aware circuit design and protection
* Design for manufacturability and yield enhancement
* Documentation and IP integration support
* Prior experience with Cadence ADE/Artist, Spectre, EMIR & reliability flows.
Note: Experience in High-speed Memory interfaces (DDR3/4/5, LPDDR5/6, GDDR5/6/7) or SerDes Interfaces (PCIe, MIPI, HDMI, USB, SATA etc) are mandatory for this role.
Show more Show less