IC
Chip Top Integrator
Accepting applicationsInnoGrit Corporation · San Jose, CA
Full-Time Mid_senior ASICArmCadenceDDRDFT
Posted
3d ago
Category
Design
Experience
Mid_senior
Country
United States
Position Summary
We are seeking a highly motivated Chip Top Integrator to support the development of complex ASIC and SoC designs from RTL integration through tapeout. The successful candidate will be responsible for integrating IPs and subsystems into the chip top, driving chip-level design quality, and collaborating with cross-functional engineering teams throughout the product development lifecycle.
The ideal candidate has a strong understanding of digital design methodologies, SoC architecture, and ASIC development flows, with hands-on experience in chip-level integration and debugging.
Key Responsibilities
Own the integration of processor, memory, interconnect, peripheral, and third-party IP blocks into the chip top-level RTL.
Develop and maintain chip top RTL, package files, parameterization, and build infrastructure.
Integrate and verify chip-level clock, reset, interrupt, power, and test connectivity.
Configure and integrate standard interfaces including AXI, AHB, APB, NoC, JTAG, GPIO, and other on-chip communication protocols.
Debug RTL integration issues including interface mismatches, parameter inconsistencies, hierarchy conflicts, and build failures.
Collaborate with IP design teams to resolve integration issues and ensure compliance with interface specifications.
Support chip-level simulation, gate-level simulation, emulation, and FPGA prototyping activities.
Work closely with verification teams to enable chip-level regressions and improve overall integration quality.
Support synthesis, lint, CDC, RDC, DFT, low-power (UPF), and timing closure by resolving integration-related issues.
Coordinate IP releases and maintain version consistency across chip development branches.
Assist firmware and software teams with memory maps, boot configuration, interrupt routing, and hardware configuration.
Develop automation scripts to improve RTL integration, regression execution, and release management.
Participate in design reviews and contribute to continuous improvement of integration methodologies and design processes.
Required Qualifications
Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
4–8 years of experience in ASIC or SoC design, integration, or verification.
Strong proficiency in Verilog and SystemVerilog.
Good understanding of SoC architecture and chip-level integration methodologies.
Experience integrating processor, memory, and peripheral IPs into complex SoCs.
Familiarity with AMBA protocols including AXI, AHB, and APB.
Experience using RTL simulation tools such as Synopsys VCS, Siemens QuestaSim, or Cadence Xcelium.
Working knowledge of synthesis, lint, CDC, RDC, DFT, and static timing analysis.
Proficiency with scripting languages such as Python, Tcl, Perl, or Shell.
Experience using version control systems such as Git or Perforce.
Strong debugging, analytical, and problem-solving skills.
Preferred Qualifications
Experience integrating Arm Cortex-A, Cortex-R, RISC-V, DSP, or accelerator-based SoCs.
Familiarity with CoreSight debug architecture, JTAG, and silicon debug infrastructure.
Experience with gate-level simulation, low-power verification, and UPF.
Knowledge of SRAM, DDR, cache subsystems, and memory controller integration.
Exposure to physical implementation concepts including floorplanning, timing closure, and ECO flows.
Experience supporting silicon bring-up and post-silicon debugging.
Desired Skills
Ability to independently manage integration tasks with minimal supervision.
Strong communication skills and the ability to work effectively across design, verification, DFT, physical design, firmware, and validation teams.
Excellent attention to detail and commitment to design quality.
Strong organizational and project management skills with the ability to prioritize multiple activities.
Continuous learning mindset with the ability to adapt to evolving technologies and methodologies.
Success Metrics
Deliver high-quality chip-level RTL integrations on schedule.
Minimize integration-related defects discovered during verification and implementation.
Successfully support synthesis, timing closure, DFT insertion, and physical design milestones.
Enable stable chip-level regressions with high pass rates.
Resolve integration issues efficiently while maintaining design quality.
Contribute automation and process improvements that increase team productivity and integration efficiency.
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We are seeking a highly motivated Chip Top Integrator to support the development of complex ASIC and SoC designs from RTL integration through tapeout. The successful candidate will be responsible for integrating IPs and subsystems into the chip top, driving chip-level design quality, and collaborating with cross-functional engineering teams throughout the product development lifecycle.
The ideal candidate has a strong understanding of digital design methodologies, SoC architecture, and ASIC development flows, with hands-on experience in chip-level integration and debugging.
Key Responsibilities
Own the integration of processor, memory, interconnect, peripheral, and third-party IP blocks into the chip top-level RTL.
Develop and maintain chip top RTL, package files, parameterization, and build infrastructure.
Integrate and verify chip-level clock, reset, interrupt, power, and test connectivity.
Configure and integrate standard interfaces including AXI, AHB, APB, NoC, JTAG, GPIO, and other on-chip communication protocols.
Debug RTL integration issues including interface mismatches, parameter inconsistencies, hierarchy conflicts, and build failures.
Collaborate with IP design teams to resolve integration issues and ensure compliance with interface specifications.
Support chip-level simulation, gate-level simulation, emulation, and FPGA prototyping activities.
Work closely with verification teams to enable chip-level regressions and improve overall integration quality.
Support synthesis, lint, CDC, RDC, DFT, low-power (UPF), and timing closure by resolving integration-related issues.
Coordinate IP releases and maintain version consistency across chip development branches.
Assist firmware and software teams with memory maps, boot configuration, interrupt routing, and hardware configuration.
Develop automation scripts to improve RTL integration, regression execution, and release management.
Participate in design reviews and contribute to continuous improvement of integration methodologies and design processes.
Required Qualifications
Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
4–8 years of experience in ASIC or SoC design, integration, or verification.
Strong proficiency in Verilog and SystemVerilog.
Good understanding of SoC architecture and chip-level integration methodologies.
Experience integrating processor, memory, and peripheral IPs into complex SoCs.
Familiarity with AMBA protocols including AXI, AHB, and APB.
Experience using RTL simulation tools such as Synopsys VCS, Siemens QuestaSim, or Cadence Xcelium.
Working knowledge of synthesis, lint, CDC, RDC, DFT, and static timing analysis.
Proficiency with scripting languages such as Python, Tcl, Perl, or Shell.
Experience using version control systems such as Git or Perforce.
Strong debugging, analytical, and problem-solving skills.
Preferred Qualifications
Experience integrating Arm Cortex-A, Cortex-R, RISC-V, DSP, or accelerator-based SoCs.
Familiarity with CoreSight debug architecture, JTAG, and silicon debug infrastructure.
Experience with gate-level simulation, low-power verification, and UPF.
Knowledge of SRAM, DDR, cache subsystems, and memory controller integration.
Exposure to physical implementation concepts including floorplanning, timing closure, and ECO flows.
Experience supporting silicon bring-up and post-silicon debugging.
Desired Skills
Ability to independently manage integration tasks with minimal supervision.
Strong communication skills and the ability to work effectively across design, verification, DFT, physical design, firmware, and validation teams.
Excellent attention to detail and commitment to design quality.
Strong organizational and project management skills with the ability to prioritize multiple activities.
Continuous learning mindset with the ability to adapt to evolving technologies and methodologies.
Success Metrics
Deliver high-quality chip-level RTL integrations on schedule.
Minimize integration-related defects discovered during verification and implementation.
Successfully support synthesis, timing closure, DFT insertion, and physical design milestones.
Enable stable chip-level regressions with high pass rates.
Resolve integration issues efficiently while maintaining design quality.
Contribute automation and process improvements that increase team productivity and integration efficiency.
Show more Show less