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Chip Design and Verification Methodology Engineer
Accepting applicationsJobright.ai · San Francisco, CA
Full-Time Mid_senior AICadencePCIePythonRTL
Posted
19h ago
Category
Verification
Experience
Mid_senior
Country
United States
This role is part of the Jobright TNT - the private hiring network connecting top talent with top AI startups like Perplexity, Mercor, Cresta, Suno and 150 more.
This is not a mass job posting. Only select, high-signal candidates are invited to Jobright TNT and recommended directly to hiring teams
Hiring Company: TenX Semi
One-liner: TenX Semi is reinventing how chips are designed to provide a seismic shift in the industry. The Chip Design and Verification Methodology Engineer will develop innovative methodologies to ensure the functional correctness of AI-generated RTL, architecting a verification loop that maximizes automation and identifies critical bugs.
Salary: $150K/yr - $300K/yr
Why Join Us:
• Build and improve AI that is redefining how next-generation chips are designed and verified while leveraging self-verifying-and-fixing loop using AI and formal methods.
• Founded by a Stanford University professor (Prof. Subhasish Mitra) and former Samsung EVP Suk Hwan Lim and a world-class team from Google, Meta, Apple, Broadcom, Stanford, Synopsys, well-funded with eight-figure backing raised from top-tier VCs.
• Work at the intersection of AI, formal verification, and chip design, one of the most technically challenging but rewarding problems in engineering.
• Join an early team with the opportunity to shape both the product and the future of AI-native chip design.
Role Responsibilities
• Drive Verification Methodology and Environment: Take responsibility for the full verification lifecycle of AI-generated design with maximal automation. You will build the verification loop that catches bugs, generates actionable feedback, and enables AI models to improve
• Architect Test Environments: Write clean, modular, and reusable verification environments/harnesses that can scale across customer designs. Your environments will integrate simulation, formal verification, and emulation into a unified flow
• Build Convergence Monitoring: Develop systems that track verification progress, measure coverage, and provide guarantees about design correctness. You will define what 'done' means for AI-generated designs
• Deep-Dive Debugging: Go beyond pass/fail logs. You will build advanced tools to read, parse, and analyze waveforms, tracing signal dependencies to pinpoint the root cause of logic failure
• Collaborate on AI Integration: Work closely with AI engineers to ensure verification feedback improves model accuracy. Your understanding of what makes RTL correct will shape how our AI learns
• Formal Proof Generation: Develop formal proofs for critical design paths, ensuring that safety-critical properties hold under all conditions
Qualifications
Required
• Verilog and SystemVerilog Fluency: You have expert-level proficiency in writing Verilog and SystemVerilog. You understand the nuances of the language for both design (RTL) and verification (TB)
• SystemVerilog Assertions: You have strong experience writing SystemVerilog Assertions. You know how to write concurrent assertions to validate complex temporal protocols
• UVM Expertise: You have deep experience with UVM methodology, including constrained-random verification, functional coverage, and scoreboards
• Computer Architecture Fundamentals: You possess a solid understanding of Computer Architecture and Digital Design fundamentals (e.g., pipelines, FSMs, clock domain crossing, memory hierarchy, and coherence protocols)
• Waveform Analysis: You have proven ability to read and analyze simulation waveforms (using tools like Verdi, SimVision, or DVE) to resolve complex logic issues
• Automation Mindset: You have strong Python/scripting skills and a passion for automating everything that can be automated
Preferred
• Hands-on experience with commercial formal tools such as JasperGold or VC Formal. Experience with formal apps (Connectivity, CDC, RDC, CSR) is highly desirable
• Deep knowledge of standard on-chip interface protocols like AXI, AHB, APB, CHI, PCIe, or CXL
• Experience at EDA vendors (Synopsys, Cadence, Siemens) or leading semiconductor companies (Intel, AMD, NVIDIA, Qualcomm)
• Familiarity with AI/ML concepts and interest in how AI can transform chip design
• MS or PhD in Electrical Engineering or Computer Science
How can I join Jobright TNT:
If this is your first time applying to a Jobright TNT role, the process works as follows:
1. Apply to your first Jobright TNT role
2. We review your background to determine if you meet the TNT quality bar
3. If qualified, your application is directly recommended to the employer
4. Once accepted into TNT, you may be:
- Invited to apply for other exclusive TNT-only roles
- Invited to private, invite-only hiring events with top startups
You will be notified of your TNT selection result.
PS: All Jobright TNT roles are 100% real, directly hired by top AI startups we partner with, and come with priority review and higher response rates than the normal application queue.
Show more Show less
This is not a mass job posting. Only select, high-signal candidates are invited to Jobright TNT and recommended directly to hiring teams
Hiring Company: TenX Semi
One-liner: TenX Semi is reinventing how chips are designed to provide a seismic shift in the industry. The Chip Design and Verification Methodology Engineer will develop innovative methodologies to ensure the functional correctness of AI-generated RTL, architecting a verification loop that maximizes automation and identifies critical bugs.
Salary: $150K/yr - $300K/yr
Why Join Us:
• Build and improve AI that is redefining how next-generation chips are designed and verified while leveraging self-verifying-and-fixing loop using AI and formal methods.
• Founded by a Stanford University professor (Prof. Subhasish Mitra) and former Samsung EVP Suk Hwan Lim and a world-class team from Google, Meta, Apple, Broadcom, Stanford, Synopsys, well-funded with eight-figure backing raised from top-tier VCs.
• Work at the intersection of AI, formal verification, and chip design, one of the most technically challenging but rewarding problems in engineering.
• Join an early team with the opportunity to shape both the product and the future of AI-native chip design.
Role Responsibilities
• Drive Verification Methodology and Environment: Take responsibility for the full verification lifecycle of AI-generated design with maximal automation. You will build the verification loop that catches bugs, generates actionable feedback, and enables AI models to improve
• Architect Test Environments: Write clean, modular, and reusable verification environments/harnesses that can scale across customer designs. Your environments will integrate simulation, formal verification, and emulation into a unified flow
• Build Convergence Monitoring: Develop systems that track verification progress, measure coverage, and provide guarantees about design correctness. You will define what 'done' means for AI-generated designs
• Deep-Dive Debugging: Go beyond pass/fail logs. You will build advanced tools to read, parse, and analyze waveforms, tracing signal dependencies to pinpoint the root cause of logic failure
• Collaborate on AI Integration: Work closely with AI engineers to ensure verification feedback improves model accuracy. Your understanding of what makes RTL correct will shape how our AI learns
• Formal Proof Generation: Develop formal proofs for critical design paths, ensuring that safety-critical properties hold under all conditions
Qualifications
Required
• Verilog and SystemVerilog Fluency: You have expert-level proficiency in writing Verilog and SystemVerilog. You understand the nuances of the language for both design (RTL) and verification (TB)
• SystemVerilog Assertions: You have strong experience writing SystemVerilog Assertions. You know how to write concurrent assertions to validate complex temporal protocols
• UVM Expertise: You have deep experience with UVM methodology, including constrained-random verification, functional coverage, and scoreboards
• Computer Architecture Fundamentals: You possess a solid understanding of Computer Architecture and Digital Design fundamentals (e.g., pipelines, FSMs, clock domain crossing, memory hierarchy, and coherence protocols)
• Waveform Analysis: You have proven ability to read and analyze simulation waveforms (using tools like Verdi, SimVision, or DVE) to resolve complex logic issues
• Automation Mindset: You have strong Python/scripting skills and a passion for automating everything that can be automated
Preferred
• Hands-on experience with commercial formal tools such as JasperGold or VC Formal. Experience with formal apps (Connectivity, CDC, RDC, CSR) is highly desirable
• Deep knowledge of standard on-chip interface protocols like AXI, AHB, APB, CHI, PCIe, or CXL
• Experience at EDA vendors (Synopsys, Cadence, Siemens) or leading semiconductor companies (Intel, AMD, NVIDIA, Qualcomm)
• Familiarity with AI/ML concepts and interest in how AI can transform chip design
• MS or PhD in Electrical Engineering or Computer Science
How can I join Jobright TNT:
If this is your first time applying to a Jobright TNT role, the process works as follows:
1. Apply to your first Jobright TNT role
2. We review your background to determine if you meet the TNT quality bar
3. If qualified, your application is directly recommended to the employer
4. Once accepted into TNT, you may be:
- Invited to apply for other exclusive TNT-only roles
- Invited to private, invite-only hiring events with top startups
You will be notified of your TNT selection result.
PS: All Jobright TNT roles are 100% real, directly hired by top AI startups we partner with, and come with priority review and higher response rates than the normal application queue.
Show more Show less