Chip analysis and verification CAD Engineer (Digital Reference flow development)

- Role Overview:
You will develop and verify the "Reference Flow" provided to customers, focusing on sign-off and verification
(STA, DRC/LVS, IRDrop/EM). We are looking for experts who can ensure the reliability of 2nm GAA designs.

- Key Responsibilities:
・Develop and validate verification steps of the Rapidus digital reference flow.
・Coordinate with EDA vendors to align tool capabilities with 2nm requirements and collaborate with design partners for flow validation.
・Create technical manuals/guidelines and provide customer support.
・Specialize in one or more: STA, Physical Verification, or Reliability Verification.

- Qualifications:
・Strong expertise in timing, physical, or reliability verification.
・Experience with advanced process nodes (7nm FinFET and beyond) is preferred but not mandatory.

(4) Chip Implementation CAD Engineer (Digital Reference Flow)
- Role Overview:
You will focus on the implementation stages (Synthesis and PnR) of the digital reference flow. Additionally,
you will lead the adoption of next-generation automation tools, including AI/ML-driven DSE(Design space exploration)

- Key Responsibilities:
・Develop and verify implementation steps (Synthesis/PnR) of the reference flow.
・Evaluate and productize AI/ML-driven Design Space Exploration (DSE) tools.
・Partner with EDA vendors to integrate the latest features and work with design contractors to streamline implementation methodologies.
・Author technical documentation and provide expert customer support.

- Qualifications:
・Experience in logic synthesis and APR (Automatic Place and Route) flows.
・Experience with advanced process nodes (7nm FinFET and beyond) is preferred but not mandatory.
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