CAD Engineer

We are seeking a CAD Engineer specializing in Digital Verification to build, enhance, and support scalable verification infrastructure, methodologies, and EDA automation flows for ASIC/SoC development.
The role focuses on enabling verification teams with robust regression systems, automation frameworks, and advanced methodologies (UVM, coverage, Continuous Integration flows) to improve productivity, debug efficiency, and time-to-tapeout.


Digital Verification CAD Support & Methodology Enablemen
tAct as the primary support interface for Design & Verification (DV) teams to troubleshoot issues in simulation, regression, coverage, and debug flow
sCollaborate with DV teams to identify bottlenecks and provide practical solutions or workaround
sSupport adoption of modern verification techniques (coverage-driven, formal, emulation) through guidance and issue resolutio
nDeploy, integrate, and maintain CAD tools, scripts, and environments supporting digital verification flow
sProvide day-to-day support for EDA tools (VCS, Xcelium, Verdi, vManager, etc.) and resolve tool/flow-related issue
sWork closely with EDA vendors (Cadence, Synopsys, Siemens) to track, debug, and escalate tool issues, and support tool evaluations and rollout
sSupport and maintain regression and CI/CD systems, ensuring stable execution and timely issue resolutio
nMonitor and optimize infrastructure usage (compute farms, LSF environments) to ensure efficient job execution and resource utilizatio
nAnalyze DV flow issues and performance bottlenecks, and provide improvements or recommendations for optimizatio
nPartner with DV, RTL design, and system teams to resolve cross-functional issues impacting verification flow
sProvide methodology guidance, user support, and training to verification engineers on tools and flow
sMaintain and contribute to documentation, best practices, and support guidelines for verification flow

s
Required Qualificatio
nsBachelor’s / master’s degree in Electronics Engineeri
ng8–12 years of experience in Digital Verification / CAD / Engineering Support-related rol
esStrong understanding of digital verification flow (simulation, regression, coverage, debu
g)Hands-on experience with System Verilog and UVM (for debugging/support perspectiv
e)Proficiency in scripting/programming (Python, Tcl, Perl, or simila
r)Experience in Linux-based environmen
tsExperience with EDA tools (VCS, Xcelium, Verdi, vManager, etc
.)Exposure to regression environments, CI/CD systems, and compute farm usa
geFamiliarity with AI/ML-based DV tools (e.g., Cadence Verisium AI) is a pl
usBasic understanding of SoC/ASIC architecture and RTL design concep

ts
Required Interpersonal Ski
llsStrong communication skills with the ability to interact effectively across te
amsProven ability to collaborate with design, verification, IT and infrastructure te
amsExperience working in multi-cultural global environments and coordinating with globally distributed te

ams
Nice-to-
HaveExposure to AI-assisted verification workflows / LLM-based tools and AI Agents developm
ent.Experience with cloud-based or distributed regression environm
entsInterest in automating repetitive support workflows across DV flows using scripting or AI-based approa
chesExperience as CAD Application Engineer in EDA vendor com

pany
Show more Show less