MT
Backend SOC Lead
Accepting applicationsMirafra Technologies · Bengaluru, Karnataka, India
Full-Time Principal CadenceCalibreFinFETGenusInnovus
Posted
1d ago
Category
Eda
Experience
Principal
Country
India
About This Job
Mirafra Technologies
Location: Bengaluru, Karnataka, India
Work Mode: On-site
Industry: Semiconductor Manufacturing,IT Services and IT Consulting
Job Description
Mirafra Techologies Hiring Backend SOC Lead
Job Title: Backend SoC Lead
Experience- 12+ years
Location: Bangalore
Key Responsibilities-
End-to-end PnR — floorplan to GDS handoff — on advanced FinFET nodes.Timing closure with AOCV / POCV across PVT corners; late-stage ECO management.Physical sign-off: DRC, LVS, ERC, power integrity (IR drop / EM).Low-power implementation: multi-voltage, power gating, retention, DVFS.Lead & mentor 5–15 backend engineers through tape-out milestones.Primary technical interface with client program teams.
Must have-
12+ years backend physical design; tapeout ownership at 16 nm or below.
Innovus or ICC2 for PnR; PrimeTime or Tempus for STA Calibre DRC / LVS sign-off and foundry rule resolution Tcl scripting for flow automation; Python a strong plusProcess nodes: TSMC 5 nmTSMC 7 nmTSMC 12 nmTSMC 16 nm Samsung 4 nm GF 12 nm GF 22FDXTSMC 22 nm.Tools : P&R Cadence Innovus, Synopsys ICC2 STA PrimeTime, Tempus Phys Ver Mentor Calibre DRC / LVS / ERC Synthesis Genus, Fusion Compiler Power Voltus, Power Artist
CPF / UPF Scripting Tcl, Python, Bash.Good communication skills.
Preferred Skills
3 nm / 2 nm node experience (TSMC N3 / N2)Chiplet / UCIe / 2.
Show more Show less
Mirafra Technologies
Location: Bengaluru, Karnataka, India
Work Mode: On-site
Industry: Semiconductor Manufacturing,IT Services and IT Consulting
Job Description
Mirafra Techologies Hiring Backend SOC Lead
Job Title: Backend SoC Lead
Experience- 12+ years
Location: Bangalore
Key Responsibilities-
End-to-end PnR — floorplan to GDS handoff — on advanced FinFET nodes.Timing closure with AOCV / POCV across PVT corners; late-stage ECO management.Physical sign-off: DRC, LVS, ERC, power integrity (IR drop / EM).Low-power implementation: multi-voltage, power gating, retention, DVFS.Lead & mentor 5–15 backend engineers through tape-out milestones.Primary technical interface with client program teams.
Must have-
12+ years backend physical design; tapeout ownership at 16 nm or below.
Innovus or ICC2 for PnR; PrimeTime or Tempus for STA Calibre DRC / LVS sign-off and foundry rule resolution Tcl scripting for flow automation; Python a strong plusProcess nodes: TSMC 5 nmTSMC 7 nmTSMC 12 nmTSMC 16 nm Samsung 4 nm GF 12 nm GF 22FDXTSMC 22 nm.Tools : P&R Cadence Innovus, Synopsys ICC2 STA PrimeTime, Tempus Phys Ver Mentor Calibre DRC / LVS / ERC Synthesis Genus, Fusion Compiler Power Voltus, Power Artist
CPF / UPF Scripting Tcl, Python, Bash.Good communication skills.
Preferred Skills
3 nm / 2 nm node experience (TSMC N3 / N2)Chiplet / UCIe / 2.
Show more Show less