U
Associate III - VLSI DFT Engineer
Accepting applicationsUST · Hyderabad, Telangana, India
Full-Time Mid_senior ATPGDFTJTAGVLSIate
Posted
4d ago
Category
Test
Experience
Mid_senior
Country
India
Role Description
We are seeking a skilled DFT Engineer with strong fundamentals and hands-on experience in test methodologies, debug, and coverage analysis. The ideal candidate will be a collaborative team player who contributes effectively to both technical execution and team growth.________________________________________Key Responsibilities
Execute and support Design-for-Test (DFT) activities including scan insertion, ATPG, and OCC integration
Perform DRC debug, test coverage analysis, and simulation debug across various stages of the DFT flow
Analyze and resolve issues related to testability, fault coverage, and pattern generation
Work with advanced DFT methodologies including SSN, IJTAG, ICL, and PDL handling
Collaborate with cross-functional teams to ensure smooth DFT integration and issue resolution
Contribute to continuous improvement of DFT flows, methodologies, and debug efficiency
________________________________________Required Skills & Experience
Strong understanding of DFT fundamentals including ATPG, scan architecture, and OCC
Proven hands-on experience in:
DRC debugo Coverage debugo Simulation debug (various modes and scenarios)
Exposure to SSN, IJTAG, ICL, and PDL frameworks
Ability to analyze complex issues and provide structured debug solutions
________________________________________Behavioral Competencies
Strong team player with a collaborative mindset
Proactive in learning and sharing knowledge within the team
Effective communication and coordination skills
Ownership-driven with focus on quality and timely delivery
Release Comments: Please do submit the candidate with 3 - 5 Years of Experience
Skills
vlsi design,dft,test methodologies,debug,coverage analysis,scan insertion,
Show more Show less
We are seeking a skilled DFT Engineer with strong fundamentals and hands-on experience in test methodologies, debug, and coverage analysis. The ideal candidate will be a collaborative team player who contributes effectively to both technical execution and team growth.________________________________________Key Responsibilities
Execute and support Design-for-Test (DFT) activities including scan insertion, ATPG, and OCC integration
Perform DRC debug, test coverage analysis, and simulation debug across various stages of the DFT flow
Analyze and resolve issues related to testability, fault coverage, and pattern generation
Work with advanced DFT methodologies including SSN, IJTAG, ICL, and PDL handling
Collaborate with cross-functional teams to ensure smooth DFT integration and issue resolution
Contribute to continuous improvement of DFT flows, methodologies, and debug efficiency
________________________________________Required Skills & Experience
Strong understanding of DFT fundamentals including ATPG, scan architecture, and OCC
Proven hands-on experience in:
DRC debugo Coverage debugo Simulation debug (various modes and scenarios)
Exposure to SSN, IJTAG, ICL, and PDL frameworks
Ability to analyze complex issues and provide structured debug solutions
________________________________________Behavioral Competencies
Strong team player with a collaborative mindset
Proactive in learning and sharing knowledge within the team
Effective communication and coordination skills
Ownership-driven with focus on quality and timely delivery
Release Comments: Please do submit the candidate with 3 - 5 Years of Experience
Skills
vlsi design,dft,test methodologies,debug,coverage analysis,scan insertion,
Show more Show less