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Associate III - VLSI

Accepting applications

UST · Bengaluru, Karnataka, India

Full-Time Entry UVMVLSIatesocverilog
Posted
6d ago
Category
Verification
Experience
Entry
Country
India
Role Description

IP verification.
Strong SV UVM skill set
DDIC subsystem.
Experience 5 + years

Skills

vlsi design,universal verification methodology,soc verification,system verilog,
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