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Associate III - VLSI Analog Layout

Accepting applications

UST · Hyderabad, Telangana, India

Full-Time Mid_senior AnalogCadenceCalibreVLSIanalog
Estimated market salary
₹21-32 LPA

This is a SiliconBoard market estimate, not an employer-posted salary.

Posted
20h ago
Category
Design
Experience
Mid_senior
Country
India
Role Description

Job Responsibilities / Day-to-Day Activities

TSMC 2nm Layout design of analog and mixed signal blocks
Floor planning, track planning, PG planning, device matching
Digital logic implementation with VSR router
DRC, LVS, Antenna, ERC PV verifications

Qualifications & Experiences:4+ years of experience

Experience with TSMC 3nm and below nodes
Well versed with Cadence latest GXL and VSR router
Well versed with Calibre PV on lower technologies
Excellent layout skills such as device matching, routing matching
Ability to design hierarchical layouts

Skills

vlsi design,analog and mixed signal,floor planning,track planning,tsmc 2nm layout design,pg planning,device matching
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