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Associate III - VLSI_ALD_N

Accepting applications

UST · Noida, Uttar Pradesh, India

Full-Time Entry AnalogCadenceRFVLSIanalog
Estimated market salary
₹12-21 LPA

This is a SiliconBoard market estimate, not an employer-posted salary.

Posted
14 Jun
Category
Design
Experience
Entry
Country
India
Role Description

Job Description:

You will be responsible for the methodology and flows development and validation in a multi-disciplinary team that covers various aspects:

Main interface with EDA partners for alignment on leading EDA vendors roadmap, critical requirements implementation and critical issues resolutions.
Deploying new methodologies and tools to all NXP R&D centers through deep collaboration and monitoring.
Providing advanced support as Application Engineer to NXP R&D centers teams when facing instabilities, issues impacting their planning or efficiency. Master s degree in Electronics Engineering, Electrical Engineering, Computer Engineering, Applied Physics or an equivalent proficiency.
Experience with AMS-RF circuit design covering Virtuoso Schematics Editor and ADE (Analog Design Environment). Exposure to analog design techniques and simulation (Cadence Assembler/Explorer).
Experience with AMS-RF design physical implementation flows from floorplan to GDS including:
Floorplan, placement, routing and verification (LVS, DRC and Antenna checks)
Experience with Cadence layout environment platform
Familiar with UNIX environment
Autonomous and possessing debug/problem-solving skills.
Excellent communication, presentation and documentation skills.
Proficient in communicating and writing technical documentation in English.
Able to work in a dynamic environment.

Considered a Plus

Experience in design migration between different foundries and nodes
Knowledge of Cadence SKILL coding language
Data Management tool, such as DesignSync Dassault

Skills

vlsi design,cadence assembler,analog design techniques,ams-rf design physical implementation,floorplan,placement
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