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Associate III - Semiconductor Product Validation

Accepting applications

UST · Hyderabad, Telangana, India

Full-Time Mid_senior ARMCadenceDDREthernetI2C
Posted
4d ago
Category
Test
Experience
Mid_senior
Country
India
Role Description

Job Description: We are seeking a seasoned Hardware Design Engineer with 4-5 years of experience to lead the development of next-generation server motherboards and high-performance compute platforms. You will own the hardware lifecycle for complex x86 (Intel/AMD) or ARM-based server architectures, ensuring robust system integration, high-speed signal integrity, and successful platform bring-up. Key Responsibilities

System Architecture & Design: Lead the architectural definition and schematic design of multi-processor server boards. Integrate complex subsystems including Chipsets (PCH), Memory (DDR4/DDR5), and High-Speed Serial Links (PCIe Gen 5/6).
Microprocessor Platform Design: Execute hardware designs for high-power CPU sockets, managing intricate pin mapping, power delivery networks (PDN), and thermal constraints.
Low-Speed IO & Management: Design and validate essential low-speed interfaces critical for server stability, including I2C/SMBus, SPI, UART, LPC, and eSPI. Manage the interface between the CPU and the Baseboard Management Controller (BMC).
Board Bring-up & Debug: Lead the "power-on" phase of new hardware. Use high-end lab equipment (DSOs, Logic Analyzers, JTAG debuggers) to root-cause complex hardware-firmware interaction issues.
Validation & Compliance: Define and execute hardware validation plans (HVP). Perform signal integrity (SI) and power integrity (PI) measurements to ensure compliance with industry standards.
Cross-Functional Leadership: Partner with BIOS/Firmware teams for power-on sequences and collaborate with Mechanical/Thermal teams to ensure the board survives high-density server environments.

Required

Technical Skills RequiredCategorySpecific Skills & ExpertiseProcessorsAMD EPYC, or high-performance platforms.High-Speed DesignPCIe (Gen 4/5/6), DDR4/DDR5, 10G/25G/100G Ethernet, SAS/SATA.Low-Speed/ControlI2C, SPI, UART, eSPI, JTAG. Debugging bus contention and timing issues.Power ManagementMulti-phase VRM design (0.8V to 12V), PMBus, and Telemetry monitoring.ToolsCadence Allegro / Concept HDL, Mentor Graphics (Xpedition), Ansys SIwave. ACADEMIC CREDENTIALS:

Bachelor's or Master's degree in electrical and electronics engineering

Skills

semiconductor product validation,x86,arm,schematic design,system architecture,cpu socketing,
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