C
ASIC Verification Lead
Accepting applicationsCadence · Noida, Uttar Pradesh, India
Full-Time Mid_senior ASICCadencePerlUVMVerilog
Estimated market salary
₹32-57 LPA
This is a SiliconBoard market estimate, not an employer-posted salary.
Posted
10 Jun
Category
Verification
Experience
Mid_senior
Country
India
Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health.
The Cadence Advantag
eThe opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact
.Cadence’s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees
.The unique “One Cadence – One Team” culture promotes collaboration within and across teams to ensure customer succes
sMultiple avenues of learning and development available for employees to explore as per their specific requirement and interest
sYou get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other—every da
y
Location: NOIDA/PU
NEBE/BTECH/ME/METCH or Equivalent Degr
eeResponsibilities
:Design Verification for interconnect IP and Tensilica Processor subsystem
s.Relevant experience in interconnect and subsystems is strongly preferr
edCrafting verification plans and executing on those plans to verify highly complex and configurable design
s.Responsible for coverage collection and closu
reWork closely with cross functional teams (DV/Arch/Design/FW) to identify coverage sco
peResponsible for creating / working with UVM based DV environmen
t.
Required Skills and Experien
ce:5+ years of design verification experie
nceBS (or higher) in EE/Computer Engineer
ingStrong technical and interpersonal ski
llsExcellent knowledge of Interconnects, NoCs and design verification fundamenta
ls.Excellent knowledge and command over AMBA protocols like AXI, AHB and A
PB.Thorough understanding of System Verilog, UVM, and other programming languages to build flexible and reusable complex testbenc
hesExposure to scripting languages like Perl, Unix shell or similar langua
gesUnderstanding of Coherency concepts will be a p
lusExperience with Formal Verification will be a p
lusExperience with development of fully automated fl
owsExperience with Gate Level Simulati
onsExcellent written and oral communication skills necess
aryExperience with integrated verification flows for processors with C and SV language is a p
lusGood experience with Simulation and Debugging tools like Cadence Xcelium, Indago e
tc.
Show more Show less
The Cadence Advantag
eThe opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact
.Cadence’s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees
.The unique “One Cadence – One Team” culture promotes collaboration within and across teams to ensure customer succes
sMultiple avenues of learning and development available for employees to explore as per their specific requirement and interest
sYou get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other—every da
y
Location: NOIDA/PU
NEBE/BTECH/ME/METCH or Equivalent Degr
eeResponsibilities
:Design Verification for interconnect IP and Tensilica Processor subsystem
s.Relevant experience in interconnect and subsystems is strongly preferr
edCrafting verification plans and executing on those plans to verify highly complex and configurable design
s.Responsible for coverage collection and closu
reWork closely with cross functional teams (DV/Arch/Design/FW) to identify coverage sco
peResponsible for creating / working with UVM based DV environmen
t.
Required Skills and Experien
ce:5+ years of design verification experie
nceBS (or higher) in EE/Computer Engineer
ingStrong technical and interpersonal ski
llsExcellent knowledge of Interconnects, NoCs and design verification fundamenta
ls.Excellent knowledge and command over AMBA protocols like AXI, AHB and A
PB.Thorough understanding of System Verilog, UVM, and other programming languages to build flexible and reusable complex testbenc
hesExposure to scripting languages like Perl, Unix shell or similar langua
gesUnderstanding of Coherency concepts will be a p
lusExperience with Formal Verification will be a p
lusExperience with development of fully automated fl
owsExperience with Gate Level Simulati
onsExcellent written and oral communication skills necess
aryExperience with integrated verification flows for processors with C and SV language is a p
lusGood experience with Simulation and Debugging tools like Cadence Xcelium, Indago e
tc.
Show more Show less
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