BS
ASIC Verification Engineer
Accepting applicationsBayOne Solutions · Sunnyvale, CA
Full-Time Mid_senior ASICCadenceMentorSoCSynopsys
Posted
19h ago
Category
Verification
Experience
Mid_senior
Country
United States
Title: ASIC Verification Engineer
Location: Sunnyvale, CA (Onsite)
Job Type: Fulltime
Salary: $180K-220K/Annum
Position Summary
We are seeking a highly motivated ASIC Verification Engineer to join our networking silicon development team.
Key Responsibilities:
Own and drive block-level or subsystem verification efforts, from creating test plans to achieving comprehensive coverage closure.
Develop, enhance, and maintain advanced UVM verification environments, including agents, sequences, scoreboards, virtual sequences, and register models.
Perform constraint-driven random testing, debug complex SoC designs, and ensure functional coverage and assertion goals are met.
Analyze simulation results using industry-leading simulation tools (e.g., Cadence Xcelium, Synopsys VCS, Mentor Questa) and debug waveforms to validate design functionality.
Collaborate with cross-functional teams to identify and resolve issues, ensuring high-quality ASIC/SoC deliverables.
Required Skills and Qualifications:
5+ years of experience in ASIC/SoC verification with a proven track record of owning verification from test plan to coverage closure.
Strong expertise in SystemVerilog and UVM methodology, including developing environments from scratch.
Deep understanding of randomization, constraints, functional coverage, and assertions (SVA).
Hands-on experience in test planning, coverage analysis, and debugging of complex SoC designs.
Proficiency with industry-standard simulation tools (e.g., Cadence Xcelium, Synopsys VCS, Mentor Questa) and waveform debugging.
Preferred Skills and Experience:
Experience verifying networking ASICs or router datapath/control blocks, such as packet processing, forwarding engines, or fabric interfaces.
Familiarity with high-speed interconnects, buffers, or scheduling pipelines in large networking SoCs.
Exposure to emulation environments, hardware acceleration, or traffic-model integration.
Knowledge of coverage analytics, regression dashboards, and continuous-integration flows (e.g., Jenkins).
Understanding of low-power (UPF) or formal verification methodologies.
Own and drive block-level/subsystem/FullChip verification efforts, from creating test plans to achieving comprehensive coverage closure
Experience with post-silicon bring-up and debug is a plus.
Familiarity with emulation environments and debug flows is desirable.
BayOne is an Equal Opportunity Employer and does not discriminate against any employee or applicant for employment because of race, color, sex, age, religion, sexual orientation, gender identity, status as a veteran, and basis of disability or any federal, state, or local protected class. This job posting represents the general duties and requirements necessary to perform this position and is not an exhaustive statement of all responsibilities, duties, and skills required. Management reserves the right to revise or alter this job description.
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Location: Sunnyvale, CA (Onsite)
Job Type: Fulltime
Salary: $180K-220K/Annum
Position Summary
We are seeking a highly motivated ASIC Verification Engineer to join our networking silicon development team.
Key Responsibilities:
Own and drive block-level or subsystem verification efforts, from creating test plans to achieving comprehensive coverage closure.
Develop, enhance, and maintain advanced UVM verification environments, including agents, sequences, scoreboards, virtual sequences, and register models.
Perform constraint-driven random testing, debug complex SoC designs, and ensure functional coverage and assertion goals are met.
Analyze simulation results using industry-leading simulation tools (e.g., Cadence Xcelium, Synopsys VCS, Mentor Questa) and debug waveforms to validate design functionality.
Collaborate with cross-functional teams to identify and resolve issues, ensuring high-quality ASIC/SoC deliverables.
Required Skills and Qualifications:
5+ years of experience in ASIC/SoC verification with a proven track record of owning verification from test plan to coverage closure.
Strong expertise in SystemVerilog and UVM methodology, including developing environments from scratch.
Deep understanding of randomization, constraints, functional coverage, and assertions (SVA).
Hands-on experience in test planning, coverage analysis, and debugging of complex SoC designs.
Proficiency with industry-standard simulation tools (e.g., Cadence Xcelium, Synopsys VCS, Mentor Questa) and waveform debugging.
Preferred Skills and Experience:
Experience verifying networking ASICs or router datapath/control blocks, such as packet processing, forwarding engines, or fabric interfaces.
Familiarity with high-speed interconnects, buffers, or scheduling pipelines in large networking SoCs.
Exposure to emulation environments, hardware acceleration, or traffic-model integration.
Knowledge of coverage analytics, regression dashboards, and continuous-integration flows (e.g., Jenkins).
Understanding of low-power (UPF) or formal verification methodologies.
Own and drive block-level/subsystem/FullChip verification efforts, from creating test plans to achieving comprehensive coverage closure
Experience with post-silicon bring-up and debug is a plus.
Familiarity with emulation environments and debug flows is desirable.
BayOne is an Equal Opportunity Employer and does not discriminate against any employee or applicant for employment because of race, color, sex, age, religion, sexual orientation, gender identity, status as a veteran, and basis of disability or any federal, state, or local protected class. This job posting represents the general duties and requirements necessary to perform this position and is not an exhaustive statement of all responsibilities, duties, and skills required. Management reserves the right to revise or alter this job description.
Show more Show less