ASIC Verification Engineer

Member of Technical Staff — ASIC Verification
Location: Santa Clara, CA or Boston, MA
Employment Type: Full-time
Workplace: On-site


About the Company

We are an early-stage startup building next-generation infrastructure for AI and datacenter workloads.

As large language models and modern AI applications continue to scale, memory movement, acceleration, and system efficiency are becoming central constraints. We are building advanced silicon and system architecture to unlock higher performance and greater efficiency for AI workloads in modern datacenters.

This is an opportunity to join early, work on a technically ambitious product, and help shape the verification foundation for a new class of high-performance computing architecture.


About the Role

We are seeking a Member of Technical Staff, ASIC Verification to help define and execute verification for silicon, IP, and subsystem development.

This role requires strong technical ownership across ASIC verification, simulation methodology, and cross-functional execution. You will help establish the verification strategy, build the methodology, drive verification closure, and ensure that complex silicon designs are ready for tapeout.

You will work closely with architecture, design, physical design, firmware, DFT, post-silicon validation, external IP vendors, foundries, and EDA partners. The role is ideal for someone who can operate hands-on while also providing technical leadership across teams and programs.


What You’ll Do
Define and implement verification methodology for IP, subsystem, and SoC-level designs
Own verification planning from microarchitecture through design implementation, simulation, closure, and tapeout
Build and maintain scalable verification environments, testbenches, checkers, scoreboards, coverage models, and regressions
Conduct design and verification reviews to ensure technical rigor and adherence to best practices
Drive functional verification, coverage closure, debug, and signoff for critical silicon blocks and subsystems
Collaborate with architecture and design teams to optimize functionality, performance, power, and area
Partner with physical design, firmware, DFT, and post-silicon teams to ensure system-level correctness and bring-up readiness
Interface with external IP vendors, foundries, and EDA tool providers to resolve dependencies and execution risks
Improve automation, scripting, and flow integration to increase verification efficiency and quality
Help establish the verification culture, standards, and technical practices for an early hardware organization


You May Be a Fit If You Have
BS or MS in Electrical Engineering, Computer Engineering, Computer Science, or a related field
5+ years of ASIC or SoC verification experience
Strong technical expertise in modern verification methodologies
Experience verifying complex IP, subsystems, or SoCs from microarchitecture through tapeout
Strong understanding of the full ASIC development lifecycle, including design, verification, physical implementation, DFT, tapeout, and post-silicon bring-up
Hands-on experience with simulation, debug, coverage closure, regression management, and verification signoff
Experience with front-end development tools, verification flows, and scripting for automation
Ability to coordinate across multiple projects, manage risks, and execute under aggressive schedules
Excellent communication, leadership, and stakeholder management skills


Strong Candidates May Also Have
PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field
Experience with SystemVerilog, UVM, constrained-random verification, assertions, formal verification, or emulation
Hands-on experience with industry-standard protocol stacks such as Ethernet, UCIe, UALink, PCIe, CXL, or related high-speed interfaces
Experience integrating and verifying major subsystems such as interconnect, I/O, memory, or accelerator blocks
Verification and tapeout experience on advanced silicon devices
Post-silicon validation or debug experience for ASICs or SoCs
Knowledge of DFT, manufacturing test, silicon debug, and production validation
Experience working with external design partners, IP vendors, foundries, and EDA tool providers
Experience optimizing designs or verification strategy around power, performance, and area goals

Why This Role Matters

AI infrastructure is increasingly constrained by memory movement, system efficiency, and the ability to translate new architecture ideas into reliable silicon.

Verification is where architectural ambition becomes silicon confidence. The methodology, environments, and signoff discipline you build will directly affect product quality, execution speed, and the company’s ability to deliver advanced hardware on aggressive timelines.

As an early member of the hardware team, you will have meaningful ownership, work with highly technical colleagues, and help build the verification foundation for the next generation of AI datacenter architecture.


The Opportunity

Impact: Help solve a fundamental infrastructure challenge: enabling greater AI capability while dramatically improving efficiency.

Timing: Join early enough to shape product direction, technical execution, and company culture.

Culture: Work with a team that values rigor, clarity, thoughtful disagreement, fast learning, and intellectual fearlessness.
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