BG
ASIC Verification
Accepting applicationsBosch Global Software Technologies · Bengaluru, Karnataka, India
Full-Time Mid_senior ARMASICMentorPerlRTL
Posted
19h ago
Category
Verification
Experience
Mid_senior
Country
India
Verification of SoCs, automotive ASICs, subsystems, IPs.
Application of Metric-driven Verification (MDV) and/or Formal Verification methodologies Developing and tracking of Verification plans
Develop verification environments from scratch
Create VIP Integration of VIP („Verification-IP“)
Measure and analyze regression results
Continuous improvement of verification methods/tools/flows/processes together with EDA partners
Requirement:5 to 10 years of Experience in Digital RTL verification using System Verilog and UVM.
Sound knowledge of constrained random verification, UVM/OVM
Sound knowledge in System Verilog.
Experience of developing functional coverage code, coverage analysis.
Experience of developing verification environments from scratch is desirable.
Good hands on experience with cadence/Synopsys/Mentor tools.
Exposure to configuration management, bug tracking tool etc.
Knowledge of scripting language, Perl TCL etc.
Good experience with AMBA protocolsWorking knowledge on ARM processor-based subsystem/SoC verification
Formal verification experience is a desirable but not must.
Must have been a part of one or more ASIC/SoC tape outs.
Knowledge of VHDL/VERILOG.SPECMAN knowledge is a desirable but not must
Qualifications
BE / B.Tech / ME / M.Tech (Electronics and Communication)
Show more Show less
Application of Metric-driven Verification (MDV) and/or Formal Verification methodologies Developing and tracking of Verification plans
Develop verification environments from scratch
Create VIP Integration of VIP („Verification-IP“)
Measure and analyze regression results
Continuous improvement of verification methods/tools/flows/processes together with EDA partners
Requirement:5 to 10 years of Experience in Digital RTL verification using System Verilog and UVM.
Sound knowledge of constrained random verification, UVM/OVM
Sound knowledge in System Verilog.
Experience of developing functional coverage code, coverage analysis.
Experience of developing verification environments from scratch is desirable.
Good hands on experience with cadence/Synopsys/Mentor tools.
Exposure to configuration management, bug tracking tool etc.
Knowledge of scripting language, Perl TCL etc.
Good experience with AMBA protocolsWorking knowledge on ARM processor-based subsystem/SoC verification
Formal verification experience is a desirable but not must.
Must have been a part of one or more ASIC/SoC tape outs.
Knowledge of VHDL/VERILOG.SPECMAN knowledge is a desirable but not must
Qualifications
BE / B.Tech / ME / M.Tech (Electronics and Communication)
Show more Show less