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ASIC Synthesis/STA & DFT Engineer
Accepting applicationsAXONNE · San Jose, CA
Full-Time Mid_senior ASICATEATPGBISTCadence
Posted
21 Aug
Category
Test
Experience
Mid_senior
Country
United States
Company Overview:
Axonne Inc. is a Silicon Valley startup that provides cutting-edge semiconductor solutions for the automotive industry with innovative in-vehicle network semiconductor solutions. We are dedicated to delivering high-performance, reliable, and state-of-the-art semiconductor products to meet the demanding requirements of automotive electronics. As we continue to grow and expand, we are seeking a dynamic and experienced ASIC Synthesis/STA & DFT Engineer to join our team and play a key role in enabling the adoption of our high-speed Ethernet semiconductor solutions in the automotive sector.
About the Role
We are looking for an experienced Front-End Design Engineer to own the RTL-to-gates flow for our ASIC/SoC designs. The ideal candidate will be a strong hands-on synthesis and static timing analysis (STA) expert who can also implement scan insertion (DFT) and memory BIST insertion, and stitch these steps into a clean, repeatable, sign-off-quality flow. This role sits between RTL design and physical implementation — you will hand off a clean, timing-constrained, DFT-ready gate-level netlist to the backend physical design team and work closely with them through timing closure. Backend place-and-route is not part of this role.
Key Responsibilities:
Own logic synthesis of RTL designs to gate-level netlists, driving timing, area, and power closure
Develop, own, and maintain SDC constraints across modes/corners; debug and resolve synthesis-stage timing violations (setup/hold, clock domain crossings, false/multicycle paths)
Build and maintain the synthesis and DFT flow — scripting, tool integration, and methodology — rather than just running an existing one
Work directly with backend physical design engineers to align constraints, handoff netlists, and resolve timing or DFT-related issues that surface during P&R
Implement scan chain insertion (scan stitching, chain balancing, lockup latches) and run ATPG to generate and grade test patterns
Insert and configure memory BIST (MBIST) IP for embedded memories (SRAM/ROM/register files), including controller integration and memory grouping
Debug DFT-related issues surfaced during ATPG, simulation, or silicon bring-up (e.g., scan test failures, BIST diagnostics)
Generate and review test coverage reports (stuck-at, transition) and drive coverage closure
Maintain flow documentation and drive automation improvements
Qualifications
Bachelor's or Master's degree in Electrical/Computer Engineering or related field
5+ years of hands-on experience in ASIC front-end flows, with strong depth in synthesis and STA
Proficiency with industry-standard synthesis tools (e.g., Synopsys Design Compiler / Fusion Compiler, Cadence Genus) and STA tools (e.g., Synopsys PrimeTime)
Demonstrated ability to construct and own a synthesis/DFT flow from scratch, not just execute an established one
Strong command of SDC constraints, timing exceptions, and multi-corner/multi-mode analysis
Hands-on experience with scan insertion and ATPG tools (e.g., Synopsys DFTMAX/TetraMAX, Siemens Tessent Scan/FastScan, Cadence Modus), including pattern generation and grading
Direct experience implementing memory BIST insertion (e.g., Siemens Tessent MemoryBIST, Synopsys STAR Memory System)
Strong scripting ability (Tcl, Python, or Perl) for flow automation
Comfortable working cross-functionally with physical design engineers on constraint and timing handoff issues
Advantageous
Experience with logic equivalence checking (LEC) tools (e.g., Synopsys Formality, Cadence Conformal)
Familiarity with ATE test program development or working with test engineering teams
Compensation
Base salary range: $160,000 – $190,000 USD
The actual starting base pay will be determined based on a variety of factors, including job-related skills, experience, qualifications, and work location. This range may be adjusted based on market conditions.
Axonne is an equal-opportunity employer. We value diversity and are committed to creating an inclusive environment for all employees.
Show more Show less
Axonne Inc. is a Silicon Valley startup that provides cutting-edge semiconductor solutions for the automotive industry with innovative in-vehicle network semiconductor solutions. We are dedicated to delivering high-performance, reliable, and state-of-the-art semiconductor products to meet the demanding requirements of automotive electronics. As we continue to grow and expand, we are seeking a dynamic and experienced ASIC Synthesis/STA & DFT Engineer to join our team and play a key role in enabling the adoption of our high-speed Ethernet semiconductor solutions in the automotive sector.
About the Role
We are looking for an experienced Front-End Design Engineer to own the RTL-to-gates flow for our ASIC/SoC designs. The ideal candidate will be a strong hands-on synthesis and static timing analysis (STA) expert who can also implement scan insertion (DFT) and memory BIST insertion, and stitch these steps into a clean, repeatable, sign-off-quality flow. This role sits between RTL design and physical implementation — you will hand off a clean, timing-constrained, DFT-ready gate-level netlist to the backend physical design team and work closely with them through timing closure. Backend place-and-route is not part of this role.
Key Responsibilities:
Own logic synthesis of RTL designs to gate-level netlists, driving timing, area, and power closure
Develop, own, and maintain SDC constraints across modes/corners; debug and resolve synthesis-stage timing violations (setup/hold, clock domain crossings, false/multicycle paths)
Build and maintain the synthesis and DFT flow — scripting, tool integration, and methodology — rather than just running an existing one
Work directly with backend physical design engineers to align constraints, handoff netlists, and resolve timing or DFT-related issues that surface during P&R
Implement scan chain insertion (scan stitching, chain balancing, lockup latches) and run ATPG to generate and grade test patterns
Insert and configure memory BIST (MBIST) IP for embedded memories (SRAM/ROM/register files), including controller integration and memory grouping
Debug DFT-related issues surfaced during ATPG, simulation, or silicon bring-up (e.g., scan test failures, BIST diagnostics)
Generate and review test coverage reports (stuck-at, transition) and drive coverage closure
Maintain flow documentation and drive automation improvements
Qualifications
Bachelor's or Master's degree in Electrical/Computer Engineering or related field
5+ years of hands-on experience in ASIC front-end flows, with strong depth in synthesis and STA
Proficiency with industry-standard synthesis tools (e.g., Synopsys Design Compiler / Fusion Compiler, Cadence Genus) and STA tools (e.g., Synopsys PrimeTime)
Demonstrated ability to construct and own a synthesis/DFT flow from scratch, not just execute an established one
Strong command of SDC constraints, timing exceptions, and multi-corner/multi-mode analysis
Hands-on experience with scan insertion and ATPG tools (e.g., Synopsys DFTMAX/TetraMAX, Siemens Tessent Scan/FastScan, Cadence Modus), including pattern generation and grading
Direct experience implementing memory BIST insertion (e.g., Siemens Tessent MemoryBIST, Synopsys STAR Memory System)
Strong scripting ability (Tcl, Python, or Perl) for flow automation
Comfortable working cross-functionally with physical design engineers on constraint and timing handoff issues
Advantageous
Experience with logic equivalence checking (LEC) tools (e.g., Synopsys Formality, Cadence Conformal)
Familiarity with ATE test program development or working with test engineering teams
Compensation
Base salary range: $160,000 – $190,000 USD
The actual starting base pay will be determined based on a variety of factors, including job-related skills, experience, qualifications, and work location. This range may be adjusted based on market conditions.
Axonne is an equal-opportunity employer. We value diversity and are committed to creating an inclusive environment for all employees.
Show more Show less