JV
ASIC/ SoC RTL Design Engineer
Accepting applicationsJobs via Dice · Palo Alto, CA
Full-Time Principal AIASICFPGARTLSoC
Posted
4d ago
Category
Design
Experience
Principal
Country
United States
Dice is the leading career destination for tech experts at every stage of their careers. Our client, Oxford Global Resources, is seeking the following. Apply via Dice today!
Title: ASIC/SoC RTL Design Engineer
Location: Palo Alto, CA (Or potentially Burlington, MA)
Length of Contract: 6 months+ (Temp-to-Perm)
Ideal Start: 6/1/2026
Responsibilities :
Own end-to-end design of complex SoC subsystems, driving architecture, RTL implementation, and tapeout. Focus on high-performance Datapath, PPA optimization, and cross-functional integration across silicon, firmware, and system teams.
Must haves:
8 12+ years in ASIC/SoC digital design with hands-on RTL ownership
Strong SystemVerilog/Verilog RTL development (Datapath, control logic, state machines)
Proven experience owning subsystems from architecture RTL tapeout
Deep understanding of PPA tradeoffs, timing closure, clock/reset, and power-aware design
Experience designing high throughput Datapath (buffering, arbitration, memory hierarchy)
Background in advanced nodes ( 28nm) and cross-functional collaboration (verification, systems, firmware)
Pluses:
Experience with compute-intensive pipelines (DSP, AI, beamforming, MAC Datapath)
Exposure to sensor / imaging systems (e.g., ultrasound, data acquisition)
Experience with programmable compute blocks (AI accelerators, MPUs, eFPGA)
Show more Show less
Title: ASIC/SoC RTL Design Engineer
Location: Palo Alto, CA (Or potentially Burlington, MA)
Length of Contract: 6 months+ (Temp-to-Perm)
Ideal Start: 6/1/2026
Responsibilities :
Own end-to-end design of complex SoC subsystems, driving architecture, RTL implementation, and tapeout. Focus on high-performance Datapath, PPA optimization, and cross-functional integration across silicon, firmware, and system teams.
Must haves:
8 12+ years in ASIC/SoC digital design with hands-on RTL ownership
Strong SystemVerilog/Verilog RTL development (Datapath, control logic, state machines)
Proven experience owning subsystems from architecture RTL tapeout
Deep understanding of PPA tradeoffs, timing closure, clock/reset, and power-aware design
Experience designing high throughput Datapath (buffering, arbitration, memory hierarchy)
Background in advanced nodes ( 28nm) and cross-functional collaboration (verification, systems, firmware)
Pluses:
Experience with compute-intensive pipelines (DSP, AI, beamforming, MAC Datapath)
Exposure to sensor / imaging systems (e.g., ultrasound, data acquisition)
Experience with programmable compute blocks (AI accelerators, MPUs, eFPGA)
Show more Show less