ASIC / SoC RTL Design Engineer

SoC RTL Design Engineer
San Jose, CA: 100% Onsite
6 + Months
$60-$62.50/HR
Role:
Lead advanced CMOS SoC design using ARM, PCIe, DDR, and Ethernet.
Responsibilities:
Architecture definition and micro-specs
RTL coding, verification, and debug
Synthesis, timing closure, and bring-up
Requirements:
ASIC design flow experience
Expert RTL coding/debugging
Desired Skills and Experience

SoC RTL Design Engineer
San Jose, CA: 100% Onsite
6 + Months
$60-$62.50/HR

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