ASIC/SoC Design & Verification Engineer

Location: United States, remote

Engagement: W-2 contingent, 20-40 hours per week

Rate: $70-$100 per hour

Overview

Mercor is hiring ASIC/SoC design and verification engineers to help evaluate and improve AI models on realistic hardware-engineering work. This role is suited for engineers who can create rigorous chip-design problems, build reference solutions, and explain model behavior clearly.

Responsibilities

Design and write realistic chip-engineering problems that reflect ASIC/SoC design and verification work.
Build reference RTL, testbenches, checkers, assertions, and supporting materials in SystemVerilog or Verilog.
Run problems against AI models, evaluate the outputs, and explain where the model succeeds or fails.
Collaborate with reviewers to keep technical content accurate, rigorous, and useful for model evaluation.

Core Qualifications

Hands-on ASIC/SoC design and/or functional verification experience; production silicon or tapeout exposure is a strong plus.
Strong SystemVerilog and Verilog skills, including RTL, microarchitecture, and testbench development.
Experience with industry or open-source verification/design tools such as Synopsys VCS, Cadence Xcelium, Siemens Questa, Verdi, VC Formal, Icarus Verilog, Verilator, CocoTB, Yosys, or OpenROAD.
Familiarity with SoC topics such as interfaces, handshaking, backpressure, multiple clock domains, and multi-module dataflow.
Depth in one or more areas such as IP integration, NoC, PCIe, DDR, ARM, AXI, UVM, SVA, CocoTB, formal verification, coverage, timing, synthesis, PPA, or analog/mixed-signal verification.
Strong written communication and ability to explain technical tradeoffs precisely.

About Mercor

Mercor connects expert professionals with projects that train and evaluate advanced AI systems.
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