ASIC/RTL Design Engineer

Pay Rate: $80.00/hr to $86.00/hr
Position: ASIC/RTL Design Engineer
Location: San Jose, CA - Onsite
Duration: 06 months Contract (possibility of extension)

Job Description:
The work will expose the designer to a number of IP including ARM cores, Ethernet, DDR, DMA, PCIE, SATA and internal IP's.
Successful candidates will be responsible for leading, and participating in, the design of leading edge SoCs in advanced digital CMOS processes.
Our RTL Design Engineers are expected contribute in all aspects of SoC design including: Chip definition, Architecture development and modeling, Development of micro-architectural specifications, Conversion of micro-architectural specifications to logic implementation, Verification, emulation, debug, synthesis, and timing closure, Interfacing with physical execution, software, and silicon bring-up teams.

Experience and Education:
SoC Architecture; knowledge and hand-on experience from industry ASIC design flow including RTL coding, debugging/verification, and supporting synthesis and timing closure.
Working knowledge of ARM cores and other I/O standard interfaces.
An ideal candidate would also exhibit: Strong communication and documentation skills, Good organizational, time management and multitasking skills, Strong initiative and discipline to follow-through, Technical leadership. 10+ years of experience.

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